base.cc revision 12406
1/* 2 * Copyright (c) 2011-2012,2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * Copyright (c) 2013 Advanced Micro Devices, Inc. 17 * Copyright (c) 2013 Mark D. Hill and David A. Wood 18 * All rights reserved. 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions are 22 * met: redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer; 24 * redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution; 27 * neither the name of the copyright holders nor the names of its 28 * contributors may be used to endorse or promote products derived from 29 * this software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * Authors: Steve Reinhardt 44 * Nathan Binkert 45 * Rick Strong 46 */ 47 48#include "cpu/base.hh" 49 50#include <iostream> 51#include <sstream> 52#include <string> 53 54#include "arch/generic/tlb.hh" 55#include "base/cprintf.hh" 56#include "base/loader/symtab.hh" 57#include "base/logging.hh" 58#include "base/output.hh" 59#include "base/trace.hh" 60#include "cpu/checker/cpu.hh" 61#include "cpu/cpuevent.hh" 62#include "cpu/profile.hh" 63#include "cpu/thread_context.hh" 64#include "debug/Mwait.hh" 65#include "debug/SyscallVerbose.hh" 66#include "mem/page_table.hh" 67#include "params/BaseCPU.hh" 68#include "sim/clocked_object.hh" 69#include "sim/full_system.hh" 70#include "sim/process.hh" 71#include "sim/sim_events.hh" 72#include "sim/sim_exit.hh" 73#include "sim/system.hh" 74 75// Hack 76#include "sim/stat_control.hh" 77 78using namespace std; 79 80vector<BaseCPU *> BaseCPU::cpuList; 81 82// This variable reflects the max number of threads in any CPU. Be 83// careful to only use it once all the CPUs that you care about have 84// been initialized 85int maxThreadsPerCPU = 1; 86 87CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 88 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 89 cpu(_cpu), _repeatEvent(true) 90{ 91 if (_interval) 92 cpu->schedule(this, curTick() + _interval); 93} 94 95void 96CPUProgressEvent::process() 97{ 98 Counter temp = cpu->totalOps(); 99 100 if (_repeatEvent) 101 cpu->schedule(this, curTick() + _interval); 102 103 if (cpu->switchedOut()) { 104 return; 105 } 106 107#ifndef NDEBUG 108 double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 109 110 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 111 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 112 ipc); 113 ipc = 0.0; 114#else 115 cprintf("%lli: %s progress event, total committed:%i, progress insts " 116 "committed: %lli\n", curTick(), cpu->name(), temp, 117 temp - lastNumInst); 118#endif 119 lastNumInst = temp; 120} 121 122const char * 123CPUProgressEvent::description() const 124{ 125 return "CPU Progress"; 126} 127 128BaseCPU::BaseCPU(Params *p, bool is_checker) 129 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 130 _instMasterId(p->system->getMasterId(name() + ".inst")), 131 _dataMasterId(p->system->getMasterId(name() + ".data")), 132 _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 133 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 134 interrupts(p->interrupts), profileEvent(NULL), 135 numThreads(p->numThreads), system(p->system), 136 previousCycle(0), previousState(CPU_STATE_SLEEP), 137 functionTraceStream(nullptr), currentFunctionStart(0), 138 currentFunctionEnd(0), functionEntryTick(0), 139 addressMonitor(p->numThreads), 140 syscallRetryLatency(p->syscallRetryLatency), 141 pwrGatingLatency(p->pwr_gating_latency), 142 powerGatingOnIdle(p->power_gating_on_idle), 143 enterPwrGatingEvent([this]{ enterPwrGating(); }, name()) 144{ 145 // if Python did not provide a valid ID, do it here 146 if (_cpuId == -1 ) { 147 _cpuId = cpuList.size(); 148 } 149 150 // add self to global list of CPUs 151 cpuList.push_back(this); 152 153 DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 154 _cpuId, _socketId); 155 156 if (numThreads > maxThreadsPerCPU) 157 maxThreadsPerCPU = numThreads; 158 159 // allocate per-thread instruction-based event queues 160 comInstEventQueue = new EventQueue *[numThreads]; 161 for (ThreadID tid = 0; tid < numThreads; ++tid) 162 comInstEventQueue[tid] = 163 new EventQueue("instruction-based event queue"); 164 165 // 166 // set up instruction-count-based termination events, if any 167 // 168 if (p->max_insts_any_thread != 0) { 169 const char *cause = "a thread reached the max instruction count"; 170 for (ThreadID tid = 0; tid < numThreads; ++tid) 171 scheduleInstStop(tid, p->max_insts_any_thread, cause); 172 } 173 174 // Set up instruction-count-based termination events for SimPoints 175 // Typically, there are more than one action points. 176 // Simulation.py is responsible to take the necessary actions upon 177 // exitting the simulation loop. 178 if (!p->simpoint_start_insts.empty()) { 179 const char *cause = "simpoint starting point found"; 180 for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 181 scheduleInstStop(0, p->simpoint_start_insts[i], cause); 182 } 183 184 if (p->max_insts_all_threads != 0) { 185 const char *cause = "all threads reached the max instruction count"; 186 187 // allocate & initialize shared downcounter: each event will 188 // decrement this when triggered; simulation will terminate 189 // when counter reaches 0 190 int *counter = new int; 191 *counter = numThreads; 192 for (ThreadID tid = 0; tid < numThreads; ++tid) { 193 Event *event = new CountedExitEvent(cause, *counter); 194 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 195 } 196 } 197 198 // allocate per-thread load-based event queues 199 comLoadEventQueue = new EventQueue *[numThreads]; 200 for (ThreadID tid = 0; tid < numThreads; ++tid) 201 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 202 203 // 204 // set up instruction-count-based termination events, if any 205 // 206 if (p->max_loads_any_thread != 0) { 207 const char *cause = "a thread reached the max load count"; 208 for (ThreadID tid = 0; tid < numThreads; ++tid) 209 scheduleLoadStop(tid, p->max_loads_any_thread, cause); 210 } 211 212 if (p->max_loads_all_threads != 0) { 213 const char *cause = "all threads reached the max load count"; 214 // allocate & initialize shared downcounter: each event will 215 // decrement this when triggered; simulation will terminate 216 // when counter reaches 0 217 int *counter = new int; 218 *counter = numThreads; 219 for (ThreadID tid = 0; tid < numThreads; ++tid) { 220 Event *event = new CountedExitEvent(cause, *counter); 221 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 222 } 223 } 224 225 functionTracingEnabled = false; 226 if (p->function_trace) { 227 const string fname = csprintf("ftrace.%s", name()); 228 functionTraceStream = simout.findOrCreate(fname)->stream(); 229 230 currentFunctionStart = currentFunctionEnd = 0; 231 functionEntryTick = p->function_trace_start; 232 233 if (p->function_trace_start == 0) { 234 functionTracingEnabled = true; 235 } else { 236 Event *event = new EventFunctionWrapper( 237 [this]{ enableFunctionTrace(); }, name(), true); 238 schedule(event, p->function_trace_start); 239 } 240 } 241 242 // The interrupts should always be present unless this CPU is 243 // switched in later or in case it is a checker CPU 244 if (!params()->switched_out && !is_checker) { 245 fatal_if(interrupts.size() != numThreads, 246 "CPU %s has %i interrupt controllers, but is expecting one " 247 "per thread (%i)\n", 248 name(), interrupts.size(), numThreads); 249 for (ThreadID tid = 0; tid < numThreads; tid++) 250 interrupts[tid]->setCPU(this); 251 } 252 253 if (FullSystem) { 254 if (params()->profile) 255 profileEvent = new EventFunctionWrapper( 256 [this]{ processProfileEvent(); }, 257 name()); 258 } 259 tracer = params()->tracer; 260 261 if (params()->isa.size() != numThreads) { 262 fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 263 "of threads (%i).\n", params()->isa.size(), numThreads); 264 } 265} 266 267void 268BaseCPU::enableFunctionTrace() 269{ 270 functionTracingEnabled = true; 271} 272 273BaseCPU::~BaseCPU() 274{ 275 delete profileEvent; 276 delete[] comLoadEventQueue; 277 delete[] comInstEventQueue; 278} 279 280void 281BaseCPU::armMonitor(ThreadID tid, Addr address) 282{ 283 assert(tid < numThreads); 284 AddressMonitor &monitor = addressMonitor[tid]; 285 286 monitor.armed = true; 287 monitor.vAddr = address; 288 monitor.pAddr = 0x0; 289 DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 290} 291 292bool 293BaseCPU::mwait(ThreadID tid, PacketPtr pkt) 294{ 295 assert(tid < numThreads); 296 AddressMonitor &monitor = addressMonitor[tid]; 297 298 if (!monitor.gotWakeup) { 299 int block_size = cacheLineSize(); 300 uint64_t mask = ~((uint64_t)(block_size - 1)); 301 302 assert(pkt->req->hasPaddr()); 303 monitor.pAddr = pkt->getAddr() & mask; 304 monitor.waiting = true; 305 306 DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 307 "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 308 return true; 309 } else { 310 monitor.gotWakeup = false; 311 return false; 312 } 313} 314 315void 316BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) 317{ 318 assert(tid < numThreads); 319 AddressMonitor &monitor = addressMonitor[tid]; 320 321 Request req; 322 Addr addr = monitor.vAddr; 323 int block_size = cacheLineSize(); 324 uint64_t mask = ~((uint64_t)(block_size - 1)); 325 int size = block_size; 326 327 //The address of the next line if it crosses a cache line boundary. 328 Addr secondAddr = roundDown(addr + size - 1, block_size); 329 330 if (secondAddr > addr) 331 size = secondAddr - addr; 332 333 req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 334 335 // translate to physical address 336 Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 337 assert(fault == NoFault); 338 339 monitor.pAddr = req.getPaddr() & mask; 340 monitor.waiting = true; 341 342 DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 343 tid, monitor.vAddr, monitor.pAddr); 344} 345 346void 347BaseCPU::init() 348{ 349 if (!params()->switched_out) { 350 registerThreadContexts(); 351 352 verifyMemoryMode(); 353 } 354} 355 356void 357BaseCPU::startup() 358{ 359 if (FullSystem) { 360 if (!params()->switched_out && profileEvent) 361 schedule(profileEvent, curTick()); 362 } 363 364 if (params()->progress_interval) { 365 new CPUProgressEvent(this, params()->progress_interval); 366 } 367 368 if (_switchedOut) 369 ClockedObject::pwrState(Enums::PwrState::OFF); 370 371 // Assumption CPU start to operate instantaneously without any latency 372 if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED) 373 ClockedObject::pwrState(Enums::PwrState::ON); 374 375} 376 377ProbePoints::PMUUPtr 378BaseCPU::pmuProbePoint(const char *name) 379{ 380 ProbePoints::PMUUPtr ptr; 381 ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 382 383 return ptr; 384} 385 386void 387BaseCPU::regProbePoints() 388{ 389 ppAllCycles = pmuProbePoint("Cycles"); 390 ppActiveCycles = pmuProbePoint("ActiveCycles"); 391 392 ppRetiredInsts = pmuProbePoint("RetiredInsts"); 393 ppRetiredLoads = pmuProbePoint("RetiredLoads"); 394 ppRetiredStores = pmuProbePoint("RetiredStores"); 395 ppRetiredBranches = pmuProbePoint("RetiredBranches"); 396 397 ppSleeping = new ProbePointArg<bool>(this->getProbeManager(), 398 "Sleeping"); 399} 400 401void 402BaseCPU::probeInstCommit(const StaticInstPtr &inst) 403{ 404 if (!inst->isMicroop() || inst->isLastMicroop()) 405 ppRetiredInsts->notify(1); 406 407 408 if (inst->isLoad()) 409 ppRetiredLoads->notify(1); 410 411 if (inst->isStore()) 412 ppRetiredStores->notify(1); 413 414 if (inst->isControl()) 415 ppRetiredBranches->notify(1); 416} 417 418void 419BaseCPU::regStats() 420{ 421 MemObject::regStats(); 422 423 using namespace Stats; 424 425 numCycles 426 .name(name() + ".numCycles") 427 .desc("number of cpu cycles simulated") 428 ; 429 430 numWorkItemsStarted 431 .name(name() + ".numWorkItemsStarted") 432 .desc("number of work items this cpu started") 433 ; 434 435 numWorkItemsCompleted 436 .name(name() + ".numWorkItemsCompleted") 437 .desc("number of work items this cpu completed") 438 ; 439 440 int size = threadContexts.size(); 441 if (size > 1) { 442 for (int i = 0; i < size; ++i) { 443 stringstream namestr; 444 ccprintf(namestr, "%s.ctx%d", name(), i); 445 threadContexts[i]->regStats(namestr.str()); 446 } 447 } else if (size == 1) 448 threadContexts[0]->regStats(name()); 449} 450 451BaseMasterPort & 452BaseCPU::getMasterPort(const string &if_name, PortID idx) 453{ 454 // Get the right port based on name. This applies to all the 455 // subclasses of the base CPU and relies on their implementation 456 // of getDataPort and getInstPort. In all cases there methods 457 // return a MasterPort pointer. 458 if (if_name == "dcache_port") 459 return getDataPort(); 460 else if (if_name == "icache_port") 461 return getInstPort(); 462 else 463 return MemObject::getMasterPort(if_name, idx); 464} 465 466void 467BaseCPU::registerThreadContexts() 468{ 469 assert(system->multiThread || numThreads == 1); 470 471 ThreadID size = threadContexts.size(); 472 for (ThreadID tid = 0; tid < size; ++tid) { 473 ThreadContext *tc = threadContexts[tid]; 474 475 if (system->multiThread) { 476 tc->setContextId(system->registerThreadContext(tc)); 477 } else { 478 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 479 } 480 481 if (!FullSystem) 482 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 483 } 484} 485 486void 487BaseCPU::deschedulePowerGatingEvent() 488{ 489 if (enterPwrGatingEvent.scheduled()){ 490 deschedule(enterPwrGatingEvent); 491 } 492} 493 494void 495BaseCPU::schedulePowerGatingEvent() 496{ 497 for (auto tc : threadContexts) { 498 if (tc->status() == ThreadContext::Active) 499 return; 500 } 501 502 if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED && 503 powerGatingOnIdle) { 504 assert(!enterPwrGatingEvent.scheduled()); 505 // Schedule a power gating event when clock gated for the specified 506 // amount of time 507 schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 508 } 509} 510 511int 512BaseCPU::findContext(ThreadContext *tc) 513{ 514 ThreadID size = threadContexts.size(); 515 for (ThreadID tid = 0; tid < size; ++tid) { 516 if (tc == threadContexts[tid]) 517 return tid; 518 } 519 return 0; 520} 521 522void 523BaseCPU::activateContext(ThreadID thread_num) 524{ 525 // Squash enter power gating event while cpu gets activated 526 if (enterPwrGatingEvent.scheduled()) 527 deschedule(enterPwrGatingEvent); 528 // For any active thread running, update CPU power state to active (ON) 529 ClockedObject::pwrState(Enums::PwrState::ON); 530 531 updateCycleCounters(CPU_STATE_WAKEUP); 532} 533 534void 535BaseCPU::suspendContext(ThreadID thread_num) 536{ 537 // Check if all threads are suspended 538 for (auto t : threadContexts) { 539 if (t->status() != ThreadContext::Suspended) { 540 return; 541 } 542 } 543 544 // All CPU thread are suspended, update cycle count 545 updateCycleCounters(CPU_STATE_SLEEP); 546 547 // All CPU threads suspended, enter lower power state for the CPU 548 ClockedObject::pwrState(Enums::PwrState::CLK_GATED); 549 550 // If pwrGatingLatency is set to 0 then this mechanism is disabled 551 if (powerGatingOnIdle) { 552 // Schedule power gating event when clock gated for pwrGatingLatency 553 // cycles 554 schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 555 } 556} 557 558void 559BaseCPU::haltContext(ThreadID thread_num) 560{ 561 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP); 562} 563 564void 565BaseCPU::enterPwrGating(void) 566{ 567 ClockedObject::pwrState(Enums::PwrState::OFF); 568} 569 570void 571BaseCPU::switchOut() 572{ 573 assert(!_switchedOut); 574 _switchedOut = true; 575 if (profileEvent && profileEvent->scheduled()) 576 deschedule(profileEvent); 577 578 // Flush all TLBs in the CPU to avoid having stale translations if 579 // it gets switched in later. 580 flushTLBs(); 581 582 // Go to the power gating state 583 ClockedObject::pwrState(Enums::PwrState::OFF); 584} 585 586void 587BaseCPU::takeOverFrom(BaseCPU *oldCPU) 588{ 589 assert(threadContexts.size() == oldCPU->threadContexts.size()); 590 assert(_cpuId == oldCPU->cpuId()); 591 assert(_switchedOut); 592 assert(oldCPU != this); 593 _pid = oldCPU->getPid(); 594 _taskId = oldCPU->taskId(); 595 // Take over the power state of the switchedOut CPU 596 ClockedObject::pwrState(oldCPU->pwrState()); 597 598 previousState = oldCPU->previousState; 599 previousCycle = oldCPU->previousCycle; 600 601 _switchedOut = false; 602 603 ThreadID size = threadContexts.size(); 604 for (ThreadID i = 0; i < size; ++i) { 605 ThreadContext *newTC = threadContexts[i]; 606 ThreadContext *oldTC = oldCPU->threadContexts[i]; 607 608 newTC->takeOverFrom(oldTC); 609 610 CpuEvent::replaceThreadContext(oldTC, newTC); 611 612 assert(newTC->contextId() == oldTC->contextId()); 613 assert(newTC->threadId() == oldTC->threadId()); 614 system->replaceThreadContext(newTC, newTC->contextId()); 615 616 /* This code no longer works since the zero register (e.g., 617 * r31 on Alpha) doesn't necessarily contain zero at this 618 * point. 619 if (DTRACE(Context)) 620 ThreadContext::compare(oldTC, newTC); 621 */ 622 623 BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 624 BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 625 BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 626 BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 627 628 // Move over any table walker ports if they exist 629 if (new_itb_port) { 630 assert(!new_itb_port->isConnected()); 631 assert(old_itb_port); 632 assert(old_itb_port->isConnected()); 633 BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 634 old_itb_port->unbind(); 635 new_itb_port->bind(slavePort); 636 } 637 if (new_dtb_port) { 638 assert(!new_dtb_port->isConnected()); 639 assert(old_dtb_port); 640 assert(old_dtb_port->isConnected()); 641 BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 642 old_dtb_port->unbind(); 643 new_dtb_port->bind(slavePort); 644 } 645 newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 646 newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 647 648 // Checker whether or not we have to transfer CheckerCPU 649 // objects over in the switch 650 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 651 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 652 if (oldChecker && newChecker) { 653 BaseMasterPort *old_checker_itb_port = 654 oldChecker->getITBPtr()->getMasterPort(); 655 BaseMasterPort *old_checker_dtb_port = 656 oldChecker->getDTBPtr()->getMasterPort(); 657 BaseMasterPort *new_checker_itb_port = 658 newChecker->getITBPtr()->getMasterPort(); 659 BaseMasterPort *new_checker_dtb_port = 660 newChecker->getDTBPtr()->getMasterPort(); 661 662 newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 663 newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 664 665 // Move over any table walker ports if they exist for checker 666 if (new_checker_itb_port) { 667 assert(!new_checker_itb_port->isConnected()); 668 assert(old_checker_itb_port); 669 assert(old_checker_itb_port->isConnected()); 670 BaseSlavePort &slavePort = 671 old_checker_itb_port->getSlavePort(); 672 old_checker_itb_port->unbind(); 673 new_checker_itb_port->bind(slavePort); 674 } 675 if (new_checker_dtb_port) { 676 assert(!new_checker_dtb_port->isConnected()); 677 assert(old_checker_dtb_port); 678 assert(old_checker_dtb_port->isConnected()); 679 BaseSlavePort &slavePort = 680 old_checker_dtb_port->getSlavePort(); 681 old_checker_dtb_port->unbind(); 682 new_checker_dtb_port->bind(slavePort); 683 } 684 } 685 } 686 687 interrupts = oldCPU->interrupts; 688 for (ThreadID tid = 0; tid < numThreads; tid++) { 689 interrupts[tid]->setCPU(this); 690 } 691 oldCPU->interrupts.clear(); 692 693 if (FullSystem) { 694 for (ThreadID i = 0; i < size; ++i) 695 threadContexts[i]->profileClear(); 696 697 if (profileEvent) 698 schedule(profileEvent, curTick()); 699 } 700 701 // All CPUs have an instruction and a data port, and the new CPU's 702 // ports are dangling while the old CPU has its ports connected 703 // already. Unbind the old CPU and then bind the ports of the one 704 // we are switching to. 705 assert(!getInstPort().isConnected()); 706 assert(oldCPU->getInstPort().isConnected()); 707 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 708 oldCPU->getInstPort().unbind(); 709 getInstPort().bind(inst_peer_port); 710 711 assert(!getDataPort().isConnected()); 712 assert(oldCPU->getDataPort().isConnected()); 713 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 714 oldCPU->getDataPort().unbind(); 715 getDataPort().bind(data_peer_port); 716} 717 718void 719BaseCPU::flushTLBs() 720{ 721 for (ThreadID i = 0; i < threadContexts.size(); ++i) { 722 ThreadContext &tc(*threadContexts[i]); 723 CheckerCPU *checker(tc.getCheckerCpuPtr()); 724 725 tc.getITBPtr()->flushAll(); 726 tc.getDTBPtr()->flushAll(); 727 if (checker) { 728 checker->getITBPtr()->flushAll(); 729 checker->getDTBPtr()->flushAll(); 730 } 731 } 732} 733 734void 735BaseCPU::processProfileEvent() 736{ 737 ThreadID size = threadContexts.size(); 738 739 for (ThreadID i = 0; i < size; ++i) 740 threadContexts[i]->profileSample(); 741 742 schedule(profileEvent, curTick() + params()->profile); 743} 744 745void 746BaseCPU::serialize(CheckpointOut &cp) const 747{ 748 SERIALIZE_SCALAR(instCnt); 749 750 if (!_switchedOut) { 751 /* Unlike _pid, _taskId is not serialized, as they are dynamically 752 * assigned unique ids that are only meaningful for the duration of 753 * a specific run. We will need to serialize the entire taskMap in 754 * system. */ 755 SERIALIZE_SCALAR(_pid); 756 757 // Serialize the threads, this is done by the CPU implementation. 758 for (ThreadID i = 0; i < numThreads; ++i) { 759 ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 760 interrupts[i]->serialize(cp); 761 serializeThread(cp, i); 762 } 763 } 764} 765 766void 767BaseCPU::unserialize(CheckpointIn &cp) 768{ 769 UNSERIALIZE_SCALAR(instCnt); 770 771 if (!_switchedOut) { 772 UNSERIALIZE_SCALAR(_pid); 773 774 // Unserialize the threads, this is done by the CPU implementation. 775 for (ThreadID i = 0; i < numThreads; ++i) { 776 ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 777 interrupts[i]->unserialize(cp); 778 unserializeThread(cp, i); 779 } 780 } 781} 782 783void 784BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 785{ 786 const Tick now(comInstEventQueue[tid]->getCurTick()); 787 Event *event(new LocalSimLoopExitEvent(cause, 0)); 788 789 comInstEventQueue[tid]->schedule(event, now + insts); 790} 791 792uint64_t 793BaseCPU::getCurrentInstCount(ThreadID tid) 794{ 795 return Tick(comInstEventQueue[tid]->getCurTick()); 796} 797 798AddressMonitor::AddressMonitor() { 799 armed = false; 800 waiting = false; 801 gotWakeup = false; 802} 803 804bool AddressMonitor::doMonitor(PacketPtr pkt) { 805 assert(pkt->req->hasPaddr()); 806 if (armed && waiting) { 807 if (pAddr == pkt->getAddr()) { 808 DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 809 pkt->getAddr()); 810 waiting = false; 811 return true; 812 } 813 } 814 return false; 815} 816 817void 818BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 819{ 820 const Tick now(comLoadEventQueue[tid]->getCurTick()); 821 Event *event(new LocalSimLoopExitEvent(cause, 0)); 822 823 comLoadEventQueue[tid]->schedule(event, now + loads); 824} 825 826 827void 828BaseCPU::traceFunctionsInternal(Addr pc) 829{ 830 if (!debugSymbolTable) 831 return; 832 833 // if pc enters different function, print new function symbol and 834 // update saved range. Otherwise do nothing. 835 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 836 string sym_str; 837 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 838 currentFunctionStart, 839 currentFunctionEnd); 840 841 if (!found) { 842 // no symbol found: use addr as label 843 sym_str = csprintf("0x%x", pc); 844 currentFunctionStart = pc; 845 currentFunctionEnd = pc + 1; 846 } 847 848 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 849 curTick() - functionEntryTick, curTick(), sym_str); 850 functionEntryTick = curTick(); 851 } 852} 853 854bool 855BaseCPU::waitForRemoteGDB() const 856{ 857 return params()->wait_for_remote_gdb; 858} 859