base.cc revision 1129
1/* 2 * Copyright (c) 2002-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <string> 30#include <sstream> 31#include <iostream> 32 33#include "cpu/base_cpu.hh" 34#include "base/cprintf.hh" 35#include "cpu/exec_context.hh" 36#include "base/misc.hh" 37#include "sim/param.hh" 38#include "sim/sim_events.hh" 39 40using namespace std; 41 42vector<BaseCPU *> BaseCPU::cpuList; 43 44// This variable reflects the max number of threads in any CPU. Be 45// careful to only use it once all the CPUs that you care about have 46// been initialized 47int maxThreadsPerCPU = 1; 48 49#ifdef FULL_SYSTEM 50BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, 51 Counter max_insts_any_thread, 52 Counter max_insts_all_threads, 53 Counter max_loads_any_thread, 54 Counter max_loads_all_threads, 55 System *_system, Tick freq) 56 : SimObject(_name), frequency(freq), deferRegistration(_def_reg), 57 number_of_threads(_number_of_threads), system(_system) 58#else 59BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, 60 Counter max_insts_any_thread, 61 Counter max_insts_all_threads, 62 Counter max_loads_any_thread, 63 Counter max_loads_all_threads) 64 : SimObject(_name), deferRegistration(_def_reg), 65 number_of_threads(_number_of_threads) 66#endif 67{ 68 // add self to global list of CPUs 69 cpuList.push_back(this); 70 71 if (number_of_threads > maxThreadsPerCPU) 72 maxThreadsPerCPU = number_of_threads; 73 74 // allocate per-thread instruction-based event queues 75 comInstEventQueue = new (EventQueue *)[number_of_threads]; 76 for (int i = 0; i < number_of_threads; ++i) 77 comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 78 79 // 80 // set up instruction-count-based termination events, if any 81 // 82 if (max_insts_any_thread != 0) 83 for (int i = 0; i < number_of_threads; ++i) 84 new SimExitEvent(comInstEventQueue[i], max_insts_any_thread, 85 "a thread reached the max instruction count"); 86 87 if (max_insts_all_threads != 0) { 88 // allocate & initialize shared downcounter: each event will 89 // decrement this when triggered; simulation will terminate 90 // when counter reaches 0 91 int *counter = new int; 92 *counter = number_of_threads; 93 for (int i = 0; i < number_of_threads; ++i) 94 new CountedExitEvent(comInstEventQueue[i], 95 "all threads reached the max instruction count", 96 max_insts_all_threads, *counter); 97 } 98 99 // allocate per-thread load-based event queues 100 comLoadEventQueue = new (EventQueue *)[number_of_threads]; 101 for (int i = 0; i < number_of_threads; ++i) 102 comLoadEventQueue[i] = new EventQueue("load-based event queue"); 103 104 // 105 // set up instruction-count-based termination events, if any 106 // 107 if (max_loads_any_thread != 0) 108 for (int i = 0; i < number_of_threads; ++i) 109 new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread, 110 "a thread reached the max load count"); 111 112 if (max_loads_all_threads != 0) { 113 // allocate & initialize shared downcounter: each event will 114 // decrement this when triggered; simulation will terminate 115 // when counter reaches 0 116 int *counter = new int; 117 *counter = number_of_threads; 118 for (int i = 0; i < number_of_threads; ++i) 119 new CountedExitEvent(comLoadEventQueue[i], 120 "all threads reached the max load count", 121 max_loads_all_threads, *counter); 122 } 123 124#ifdef FULL_SYSTEM 125 memset(interrupts, 0, sizeof(interrupts)); 126 intstatus = 0; 127#endif 128} 129 130void 131BaseCPU::init() 132{ 133 if (!deferRegistration) 134 registerExecContexts(); 135} 136 137void 138BaseCPU::regStats() 139{ 140 using namespace Stats; 141 142 numCycles 143 .name(name() + ".numCycles") 144 .desc("number of cpu cycles simulated") 145 ; 146 147 int size = execContexts.size(); 148 if (size > 1) { 149 for (int i = 0; i < size; ++i) { 150 stringstream namestr; 151 ccprintf(namestr, "%s.ctx%d", name(), i); 152 execContexts[i]->regStats(namestr.str()); 153 } 154 } else if (size == 1) 155 execContexts[0]->regStats(name()); 156} 157 158 159void 160BaseCPU::registerExecContexts() 161{ 162 for (int i = 0; i < execContexts.size(); ++i) { 163 ExecContext *xc = execContexts[i]; 164 int cpu_id; 165 166#ifdef FULL_SYSTEM 167 cpu_id = system->registerExecContext(xc); 168#else 169 cpu_id = xc->process->registerExecContext(xc); 170#endif 171 172 xc->cpu_id = cpu_id; 173 } 174} 175 176 177void 178BaseCPU::switchOut() 179{ 180 // default: do nothing 181} 182 183void 184BaseCPU::takeOverFrom(BaseCPU *oldCPU) 185{ 186 assert(execContexts.size() == oldCPU->execContexts.size()); 187 188 for (int i = 0; i < execContexts.size(); ++i) { 189 ExecContext *newXC = execContexts[i]; 190 ExecContext *oldXC = oldCPU->execContexts[i]; 191 192 newXC->takeOverFrom(oldXC); 193 assert(newXC->cpu_id == oldXC->cpu_id); 194#ifdef FULL_SYSTEM 195 system->replaceExecContext(newXC, newXC->cpu_id); 196#else 197 assert(newXC->process == oldXC->process); 198 newXC->process->replaceExecContext(newXC, newXC->cpu_id); 199#endif 200 } 201 202#ifdef FULL_SYSTEM 203 for (int i = 0; i < NumInterruptLevels; ++i) 204 interrupts[i] = oldCPU->interrupts[i]; 205 intstatus = oldCPU->intstatus; 206#endif 207} 208 209 210#ifdef FULL_SYSTEM 211void 212BaseCPU::post_interrupt(int int_num, int index) 213{ 214 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 215 216 if (int_num < 0 || int_num >= NumInterruptLevels) 217 panic("int_num out of bounds\n"); 218 219 if (index < 0 || index >= sizeof(uint64_t) * 8) 220 panic("int_num out of bounds\n"); 221 222 AlphaISA::check_interrupts = 1; 223 interrupts[int_num] |= 1 << index; 224 intstatus |= (ULL(1) << int_num); 225} 226 227void 228BaseCPU::clear_interrupt(int int_num, int index) 229{ 230 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 231 232 if (int_num < 0 || int_num >= NumInterruptLevels) 233 panic("int_num out of bounds\n"); 234 235 if (index < 0 || index >= sizeof(uint64_t) * 8) 236 panic("int_num out of bounds\n"); 237 238 interrupts[int_num] &= ~(1 << index); 239 if (interrupts[int_num] == 0) 240 intstatus &= ~(ULL(1) << int_num); 241} 242 243void 244BaseCPU::clear_interrupts() 245{ 246 DPRINTF(Interrupt, "Interrupts all cleared\n"); 247 248 memset(interrupts, 0, sizeof(interrupts)); 249 intstatus = 0; 250} 251 252 253void 254BaseCPU::serialize(std::ostream &os) 255{ 256 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 257 SERIALIZE_SCALAR(intstatus); 258} 259 260void 261BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 262{ 263 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 264 UNSERIALIZE_SCALAR(intstatus); 265} 266 267#endif // FULL_SYSTEM 268 269DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 270