base.cc revision 10061
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * Copyright (c) 2013 Advanced Micro Devices, Inc. 17 * Copyright (c) 2013 Mark D. Hill and David A. Wood 18 * All rights reserved. 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions are 22 * met: redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer; 24 * redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution; 27 * neither the name of the copyright holders nor the names of its 28 * contributors may be used to endorse or promote products derived from 29 * this software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * Authors: Steve Reinhardt 44 * Nathan Binkert 45 * Rick Strong 46 */ 47 48#include <iostream> 49#include <sstream> 50#include <string> 51 52#include "arch/tlb.hh" 53#include "base/loader/symtab.hh" 54#include "base/cprintf.hh" 55#include "base/misc.hh" 56#include "base/output.hh" 57#include "base/trace.hh" 58#include "cpu/base.hh" 59#include "cpu/checker/cpu.hh" 60#include "cpu/cpuevent.hh" 61#include "cpu/profile.hh" 62#include "cpu/thread_context.hh" 63#include "debug/SyscallVerbose.hh" 64#include "params/BaseCPU.hh" 65#include "sim/full_system.hh" 66#include "sim/process.hh" 67#include "sim/sim_events.hh" 68#include "sim/sim_exit.hh" 69#include "sim/system.hh" 70 71// Hack 72#include "sim/stat_control.hh" 73 74using namespace std; 75 76vector<BaseCPU *> BaseCPU::cpuList; 77 78// This variable reflects the max number of threads in any CPU. Be 79// careful to only use it once all the CPUs that you care about have 80// been initialized 81int maxThreadsPerCPU = 1; 82 83CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 84 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 85 cpu(_cpu), _repeatEvent(true) 86{ 87 if (_interval) 88 cpu->schedule(this, curTick() + _interval); 89} 90 91void 92CPUProgressEvent::process() 93{ 94 Counter temp = cpu->totalOps(); 95#ifndef NDEBUG 96 double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 97 98 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 99 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 100 ipc); 101 ipc = 0.0; 102#else 103 cprintf("%lli: %s progress event, total committed:%i, progress insts " 104 "committed: %lli\n", curTick(), cpu->name(), temp, 105 temp - lastNumInst); 106#endif 107 lastNumInst = temp; 108 109 if (_repeatEvent) 110 cpu->schedule(this, curTick() + _interval); 111} 112 113const char * 114CPUProgressEvent::description() const 115{ 116 return "CPU Progress"; 117} 118 119BaseCPU::BaseCPU(Params *p, bool is_checker) 120 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 121 _instMasterId(p->system->getMasterId(name() + ".inst")), 122 _dataMasterId(p->system->getMasterId(name() + ".data")), 123 _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 124 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 125 interrupts(p->interrupts), profileEvent(NULL), 126 numThreads(p->numThreads), system(p->system) 127{ 128 // if Python did not provide a valid ID, do it here 129 if (_cpuId == -1 ) { 130 _cpuId = cpuList.size(); 131 } 132 133 // add self to global list of CPUs 134 cpuList.push_back(this); 135 136 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 137 138 if (numThreads > maxThreadsPerCPU) 139 maxThreadsPerCPU = numThreads; 140 141 // allocate per-thread instruction-based event queues 142 comInstEventQueue = new EventQueue *[numThreads]; 143 for (ThreadID tid = 0; tid < numThreads; ++tid) 144 comInstEventQueue[tid] = 145 new EventQueue("instruction-based event queue"); 146 147 // 148 // set up instruction-count-based termination events, if any 149 // 150 if (p->max_insts_any_thread != 0) { 151 const char *cause = "a thread reached the max instruction count"; 152 for (ThreadID tid = 0; tid < numThreads; ++tid) 153 scheduleInstStop(tid, p->max_insts_any_thread, cause); 154 } 155 156 // Set up instruction-count-based termination events for SimPoints 157 // Typically, there are more than one action points. 158 // Simulation.py is responsible to take the necessary actions upon 159 // exitting the simulation loop. 160 if (!p->simpoint_start_insts.empty()) { 161 const char *cause = "simpoint starting point found"; 162 for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 163 scheduleInstStop(0, p->simpoint_start_insts[i], cause); 164 } 165 166 if (p->max_insts_all_threads != 0) { 167 const char *cause = "all threads reached the max instruction count"; 168 169 // allocate & initialize shared downcounter: each event will 170 // decrement this when triggered; simulation will terminate 171 // when counter reaches 0 172 int *counter = new int; 173 *counter = numThreads; 174 for (ThreadID tid = 0; tid < numThreads; ++tid) { 175 Event *event = new CountedExitEvent(cause, *counter); 176 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 177 } 178 } 179 180 // allocate per-thread load-based event queues 181 comLoadEventQueue = new EventQueue *[numThreads]; 182 for (ThreadID tid = 0; tid < numThreads; ++tid) 183 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 184 185 // 186 // set up instruction-count-based termination events, if any 187 // 188 if (p->max_loads_any_thread != 0) { 189 const char *cause = "a thread reached the max load count"; 190 for (ThreadID tid = 0; tid < numThreads; ++tid) 191 scheduleLoadStop(tid, p->max_loads_any_thread, cause); 192 } 193 194 if (p->max_loads_all_threads != 0) { 195 const char *cause = "all threads reached the max load count"; 196 // allocate & initialize shared downcounter: each event will 197 // decrement this when triggered; simulation will terminate 198 // when counter reaches 0 199 int *counter = new int; 200 *counter = numThreads; 201 for (ThreadID tid = 0; tid < numThreads; ++tid) { 202 Event *event = new CountedExitEvent(cause, *counter); 203 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 204 } 205 } 206 207 functionTracingEnabled = false; 208 if (p->function_trace) { 209 const string fname = csprintf("ftrace.%s", name()); 210 functionTraceStream = simout.find(fname); 211 if (!functionTraceStream) 212 functionTraceStream = simout.create(fname); 213 214 currentFunctionStart = currentFunctionEnd = 0; 215 functionEntryTick = p->function_trace_start; 216 217 if (p->function_trace_start == 0) { 218 functionTracingEnabled = true; 219 } else { 220 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 221 Event *event = new wrap(this, true); 222 schedule(event, p->function_trace_start); 223 } 224 } 225 226 // The interrupts should always be present unless this CPU is 227 // switched in later or in case it is a checker CPU 228 if (!params()->switched_out && !is_checker) { 229 if (interrupts) { 230 interrupts->setCPU(this); 231 } else { 232 fatal("CPU %s has no interrupt controller.\n" 233 "Ensure createInterruptController() is called.\n", name()); 234 } 235 } 236 237 if (FullSystem) { 238 if (params()->profile) 239 profileEvent = new ProfileEvent(this, params()->profile); 240 } 241 tracer = params()->tracer; 242 243 if (params()->isa.size() != numThreads) { 244 fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 245 "of threads (%i).\n", params()->isa.size(), numThreads); 246 } 247} 248 249void 250BaseCPU::enableFunctionTrace() 251{ 252 functionTracingEnabled = true; 253} 254 255BaseCPU::~BaseCPU() 256{ 257 delete profileEvent; 258 delete[] comLoadEventQueue; 259 delete[] comInstEventQueue; 260} 261 262void 263BaseCPU::init() 264{ 265 if (!params()->switched_out) { 266 registerThreadContexts(); 267 268 verifyMemoryMode(); 269 } 270} 271 272void 273BaseCPU::startup() 274{ 275 if (FullSystem) { 276 if (!params()->switched_out && profileEvent) 277 schedule(profileEvent, curTick()); 278 } 279 280 if (params()->progress_interval) { 281 new CPUProgressEvent(this, params()->progress_interval); 282 } 283} 284 285 286void 287BaseCPU::regStats() 288{ 289 using namespace Stats; 290 291 numCycles 292 .name(name() + ".numCycles") 293 .desc("number of cpu cycles simulated") 294 ; 295 296 numWorkItemsStarted 297 .name(name() + ".numWorkItemsStarted") 298 .desc("number of work items this cpu started") 299 ; 300 301 numWorkItemsCompleted 302 .name(name() + ".numWorkItemsCompleted") 303 .desc("number of work items this cpu completed") 304 ; 305 306 int size = threadContexts.size(); 307 if (size > 1) { 308 for (int i = 0; i < size; ++i) { 309 stringstream namestr; 310 ccprintf(namestr, "%s.ctx%d", name(), i); 311 threadContexts[i]->regStats(namestr.str()); 312 } 313 } else if (size == 1) 314 threadContexts[0]->regStats(name()); 315} 316 317BaseMasterPort & 318BaseCPU::getMasterPort(const string &if_name, PortID idx) 319{ 320 // Get the right port based on name. This applies to all the 321 // subclasses of the base CPU and relies on their implementation 322 // of getDataPort and getInstPort. In all cases there methods 323 // return a MasterPort pointer. 324 if (if_name == "dcache_port") 325 return getDataPort(); 326 else if (if_name == "icache_port") 327 return getInstPort(); 328 else 329 return MemObject::getMasterPort(if_name, idx); 330} 331 332void 333BaseCPU::registerThreadContexts() 334{ 335 ThreadID size = threadContexts.size(); 336 for (ThreadID tid = 0; tid < size; ++tid) { 337 ThreadContext *tc = threadContexts[tid]; 338 339 /** This is so that contextId and cpuId match where there is a 340 * 1cpu:1context relationship. Otherwise, the order of registration 341 * could affect the assignment and cpu 1 could have context id 3, for 342 * example. We may even want to do something like this for SMT so that 343 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 344 * I'll just do this for now 345 */ 346 if (numThreads == 1) 347 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 348 else 349 tc->setContextId(system->registerThreadContext(tc)); 350 351 if (!FullSystem) 352 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 353 } 354} 355 356 357int 358BaseCPU::findContext(ThreadContext *tc) 359{ 360 ThreadID size = threadContexts.size(); 361 for (ThreadID tid = 0; tid < size; ++tid) { 362 if (tc == threadContexts[tid]) 363 return tid; 364 } 365 return 0; 366} 367 368void 369BaseCPU::switchOut() 370{ 371 assert(!_switchedOut); 372 _switchedOut = true; 373 if (profileEvent && profileEvent->scheduled()) 374 deschedule(profileEvent); 375 376 // Flush all TLBs in the CPU to avoid having stale translations if 377 // it gets switched in later. 378 flushTLBs(); 379} 380 381void 382BaseCPU::takeOverFrom(BaseCPU *oldCPU) 383{ 384 assert(threadContexts.size() == oldCPU->threadContexts.size()); 385 assert(_cpuId == oldCPU->cpuId()); 386 assert(_switchedOut); 387 assert(oldCPU != this); 388 _pid = oldCPU->getPid(); 389 _taskId = oldCPU->taskId(); 390 _switchedOut = false; 391 392 ThreadID size = threadContexts.size(); 393 for (ThreadID i = 0; i < size; ++i) { 394 ThreadContext *newTC = threadContexts[i]; 395 ThreadContext *oldTC = oldCPU->threadContexts[i]; 396 397 newTC->takeOverFrom(oldTC); 398 399 CpuEvent::replaceThreadContext(oldTC, newTC); 400 401 assert(newTC->contextId() == oldTC->contextId()); 402 assert(newTC->threadId() == oldTC->threadId()); 403 system->replaceThreadContext(newTC, newTC->contextId()); 404 405 /* This code no longer works since the zero register (e.g., 406 * r31 on Alpha) doesn't necessarily contain zero at this 407 * point. 408 if (DTRACE(Context)) 409 ThreadContext::compare(oldTC, newTC); 410 */ 411 412 BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 413 BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 414 BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 415 BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 416 417 // Move over any table walker ports if they exist 418 if (new_itb_port) { 419 assert(!new_itb_port->isConnected()); 420 assert(old_itb_port); 421 assert(old_itb_port->isConnected()); 422 BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 423 old_itb_port->unbind(); 424 new_itb_port->bind(slavePort); 425 } 426 if (new_dtb_port) { 427 assert(!new_dtb_port->isConnected()); 428 assert(old_dtb_port); 429 assert(old_dtb_port->isConnected()); 430 BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 431 old_dtb_port->unbind(); 432 new_dtb_port->bind(slavePort); 433 } 434 435 // Checker whether or not we have to transfer CheckerCPU 436 // objects over in the switch 437 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 438 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 439 if (oldChecker && newChecker) { 440 BaseMasterPort *old_checker_itb_port = 441 oldChecker->getITBPtr()->getMasterPort(); 442 BaseMasterPort *old_checker_dtb_port = 443 oldChecker->getDTBPtr()->getMasterPort(); 444 BaseMasterPort *new_checker_itb_port = 445 newChecker->getITBPtr()->getMasterPort(); 446 BaseMasterPort *new_checker_dtb_port = 447 newChecker->getDTBPtr()->getMasterPort(); 448 449 // Move over any table walker ports if they exist for checker 450 if (new_checker_itb_port) { 451 assert(!new_checker_itb_port->isConnected()); 452 assert(old_checker_itb_port); 453 assert(old_checker_itb_port->isConnected()); 454 BaseSlavePort &slavePort = 455 old_checker_itb_port->getSlavePort(); 456 old_checker_itb_port->unbind(); 457 new_checker_itb_port->bind(slavePort); 458 } 459 if (new_checker_dtb_port) { 460 assert(!new_checker_dtb_port->isConnected()); 461 assert(old_checker_dtb_port); 462 assert(old_checker_dtb_port->isConnected()); 463 BaseSlavePort &slavePort = 464 old_checker_dtb_port->getSlavePort(); 465 old_checker_dtb_port->unbind(); 466 new_checker_dtb_port->bind(slavePort); 467 } 468 } 469 } 470 471 interrupts = oldCPU->interrupts; 472 interrupts->setCPU(this); 473 oldCPU->interrupts = NULL; 474 475 if (FullSystem) { 476 for (ThreadID i = 0; i < size; ++i) 477 threadContexts[i]->profileClear(); 478 479 if (profileEvent) 480 schedule(profileEvent, curTick()); 481 } 482 483 // All CPUs have an instruction and a data port, and the new CPU's 484 // ports are dangling while the old CPU has its ports connected 485 // already. Unbind the old CPU and then bind the ports of the one 486 // we are switching to. 487 assert(!getInstPort().isConnected()); 488 assert(oldCPU->getInstPort().isConnected()); 489 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 490 oldCPU->getInstPort().unbind(); 491 getInstPort().bind(inst_peer_port); 492 493 assert(!getDataPort().isConnected()); 494 assert(oldCPU->getDataPort().isConnected()); 495 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 496 oldCPU->getDataPort().unbind(); 497 getDataPort().bind(data_peer_port); 498} 499 500void 501BaseCPU::flushTLBs() 502{ 503 for (ThreadID i = 0; i < threadContexts.size(); ++i) { 504 ThreadContext &tc(*threadContexts[i]); 505 CheckerCPU *checker(tc.getCheckerCpuPtr()); 506 507 tc.getITBPtr()->flushAll(); 508 tc.getDTBPtr()->flushAll(); 509 if (checker) { 510 checker->getITBPtr()->flushAll(); 511 checker->getDTBPtr()->flushAll(); 512 } 513 } 514} 515 516 517BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 518 : cpu(_cpu), interval(_interval) 519{ } 520 521void 522BaseCPU::ProfileEvent::process() 523{ 524 ThreadID size = cpu->threadContexts.size(); 525 for (ThreadID i = 0; i < size; ++i) { 526 ThreadContext *tc = cpu->threadContexts[i]; 527 tc->profileSample(); 528 } 529 530 cpu->schedule(this, curTick() + interval); 531} 532 533void 534BaseCPU::serialize(std::ostream &os) 535{ 536 SERIALIZE_SCALAR(instCnt); 537 538 if (!_switchedOut) { 539 /* Unlike _pid, _taskId is not serialized, as they are dynamically 540 * assigned unique ids that are only meaningful for the duration of 541 * a specific run. We will need to serialize the entire taskMap in 542 * system. */ 543 SERIALIZE_SCALAR(_pid); 544 545 interrupts->serialize(os); 546 547 // Serialize the threads, this is done by the CPU implementation. 548 for (ThreadID i = 0; i < numThreads; ++i) { 549 nameOut(os, csprintf("%s.xc.%i", name(), i)); 550 serializeThread(os, i); 551 } 552 } 553} 554 555void 556BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 557{ 558 UNSERIALIZE_SCALAR(instCnt); 559 560 if (!_switchedOut) { 561 UNSERIALIZE_SCALAR(_pid); 562 interrupts->unserialize(cp, section); 563 564 // Unserialize the threads, this is done by the CPU implementation. 565 for (ThreadID i = 0; i < numThreads; ++i) 566 unserializeThread(cp, csprintf("%s.xc.%i", section, i), i); 567 } 568} 569 570void 571BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 572{ 573 const Tick now(comInstEventQueue[tid]->getCurTick()); 574 Event *event(new LocalSimLoopExitEvent(cause, 0)); 575 576 comInstEventQueue[tid]->schedule(event, now + insts); 577} 578 579void 580BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 581{ 582 const Tick now(comLoadEventQueue[tid]->getCurTick()); 583 Event *event(new LocalSimLoopExitEvent(cause, 0)); 584 585 comLoadEventQueue[tid]->schedule(event, now + loads); 586} 587 588 589void 590BaseCPU::traceFunctionsInternal(Addr pc) 591{ 592 if (!debugSymbolTable) 593 return; 594 595 // if pc enters different function, print new function symbol and 596 // update saved range. Otherwise do nothing. 597 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 598 string sym_str; 599 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 600 currentFunctionStart, 601 currentFunctionEnd); 602 603 if (!found) { 604 // no symbol found: use addr as label 605 sym_str = csprintf("0x%x", pc); 606 currentFunctionStart = pc; 607 currentFunctionEnd = pc + 1; 608 } 609 610 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 611 curTick() - functionEntryTick, curTick(), sym_str); 612 functionEntryTick = curTick(); 613 } 614} 615