base.cc revision 9384
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 561717SN/A#include "cpu/base.hh" 578887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642190SN/A#include "sim/process.hh" 6556SN/A#include "sim/sim_events.hh" 668229Snate@binkert.org#include "sim/sim_exit.hh" 672190SN/A#include "sim/system.hh" 682SN/A 692359SN/A// Hack 702359SN/A#include "sim/stat_control.hh" 712359SN/A 722SN/Ausing namespace std; 732SN/A 742SN/Avector<BaseCPU *> BaseCPU::cpuList; 752SN/A 762SN/A// This variable reflects the max number of threads in any CPU. Be 772SN/A// careful to only use it once all the CPUs that you care about have 782SN/A// been initialized 792SN/Aint maxThreadsPerCPU = 1; 802SN/A 815606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 826144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 836144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 843126Sktlim@umich.edu{ 856144Sksewell@umich.edu if (_interval) 867823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 873126Sktlim@umich.edu} 883126Sktlim@umich.edu 892356SN/Avoid 902356SN/ACPUProgressEvent::process() 912356SN/A{ 928834Satgutier@umich.edu Counter temp = cpu->totalOps(); 932356SN/A#ifndef NDEBUG 949179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 952367SN/A 966144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 976144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 986144Sksewell@umich.edu ipc); 992356SN/A ipc = 0.0; 1002367SN/A#else 1016144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1027823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1036144Sksewell@umich.edu temp - lastNumInst); 1042367SN/A#endif 1052356SN/A lastNumInst = temp; 1066144Sksewell@umich.edu 1076144Sksewell@umich.edu if (_repeatEvent) 1087823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1092356SN/A} 1102356SN/A 1112356SN/Aconst char * 1125336Shines@cs.fsu.eduCPUProgressEvent::description() const 1132356SN/A{ 1144873Sstever@eecs.umich.edu return "CPU Progress"; 1152356SN/A} 1162356SN/A 1178876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 1189157Sandreas.hansson@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 1198832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1208832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1219332Sdam.sunwoo@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 1229220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 1239157Sandreas.hansson@arm.com numThreads(p->numThreads), system(p->system) 1242SN/A{ 1255712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1265712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1275712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1285712Shsul@eecs.umich.edu } 1295712Shsul@eecs.umich.edu 1302SN/A // add self to global list of CPUs 1312SN/A cpuList.push_back(this); 1322SN/A 1335712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1345712Shsul@eecs.umich.edu 1356221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1366221Snate@binkert.org maxThreadsPerCPU = numThreads; 1372SN/A 1382SN/A // allocate per-thread instruction-based event queues 1396221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1416221Snate@binkert.org comInstEventQueue[tid] = 1426221Snate@binkert.org new EventQueue("instruction-based event queue"); 1432SN/A 1442SN/A // 1452SN/A // set up instruction-count-based termination events, if any 1462SN/A // 1475606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1485606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1496221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1505606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1516221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1525606Snate@binkert.org } 1535606Snate@binkert.org } 1542SN/A 1551400SN/A if (p->max_insts_all_threads != 0) { 1565606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1575606Snate@binkert.org 1582SN/A // allocate & initialize shared downcounter: each event will 1592SN/A // decrement this when triggered; simulation will terminate 1602SN/A // when counter reaches 0 1612SN/A int *counter = new int; 1626221Snate@binkert.org *counter = numThreads; 1636221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1645606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1656670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1665606Snate@binkert.org } 1672SN/A } 1682SN/A 169124SN/A // allocate per-thread load-based event queues 1706221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1716221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1726221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 173124SN/A 174124SN/A // 175124SN/A // set up instruction-count-based termination events, if any 176124SN/A // 1775606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1785606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1796221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1805606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1816221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1825606Snate@binkert.org } 1835606Snate@binkert.org } 184124SN/A 1851400SN/A if (p->max_loads_all_threads != 0) { 1865606Snate@binkert.org const char *cause = "all threads reached the max load count"; 187124SN/A // allocate & initialize shared downcounter: each event will 188124SN/A // decrement this when triggered; simulation will terminate 189124SN/A // when counter reaches 0 190124SN/A int *counter = new int; 1916221Snate@binkert.org *counter = numThreads; 1926221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1935606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1946221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 1955606Snate@binkert.org } 196124SN/A } 197124SN/A 1981191SN/A functionTracingEnabled = false; 1995529Snate@binkert.org if (p->function_trace) { 2008634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2018634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2028634Schris.emmons@arm.com if (!functionTraceStream) 2038634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2048634Schris.emmons@arm.com 2051191SN/A currentFunctionStart = currentFunctionEnd = 0; 2065529Snate@binkert.org functionEntryTick = p->function_trace_start; 2071191SN/A 2085529Snate@binkert.org if (p->function_trace_start == 0) { 2091191SN/A functionTracingEnabled = true; 2101191SN/A } else { 2115606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2125606Snate@binkert.org Event *event = new wrap(this, true); 2135606Snate@binkert.org schedule(event, p->function_trace_start); 2141191SN/A } 2151191SN/A } 2168876Sandreas.hansson@arm.com 2178876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2188876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2198876Sandreas.hansson@arm.com if (!params()->defer_registration && !is_checker) { 2208876Sandreas.hansson@arm.com if (interrupts) { 2218876Sandreas.hansson@arm.com interrupts->setCPU(this); 2228876Sandreas.hansson@arm.com } else { 2238876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2248876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2258876Sandreas.hansson@arm.com } 2268876Sandreas.hansson@arm.com } 2275810Sgblack@eecs.umich.edu 2288779Sgblack@eecs.umich.edu if (FullSystem) { 2298779Sgblack@eecs.umich.edu if (params()->profile) 2308779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2318779Sgblack@eecs.umich.edu } 2325529Snate@binkert.org tracer = params()->tracer; 2339384SAndreas.Sandberg@arm.com 2349384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2359384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2369384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2379384SAndreas.Sandberg@arm.com } 2381917SN/A} 2391191SN/A 2401191SN/Avoid 2411191SN/ABaseCPU::enableFunctionTrace() 2421191SN/A{ 2431191SN/A functionTracingEnabled = true; 2441191SN/A} 2451191SN/A 2461191SN/ABaseCPU::~BaseCPU() 2471191SN/A{ 2489086Sandreas.hansson@arm.com delete profileEvent; 2499086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2509086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2511191SN/A} 2521191SN/A 2531129SN/Avoid 2541129SN/ABaseCPU::init() 2551129SN/A{ 2565529Snate@binkert.org if (!params()->defer_registration) 2572680Sktlim@umich.edu registerThreadContexts(); 2581129SN/A} 259180SN/A 2602SN/Avoid 2611917SN/ABaseCPU::startup() 2621917SN/A{ 2638779Sgblack@eecs.umich.edu if (FullSystem) { 2648779Sgblack@eecs.umich.edu if (!params()->defer_registration && profileEvent) 2658779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2668779Sgblack@eecs.umich.edu } 2672356SN/A 2685529Snate@binkert.org if (params()->progress_interval) { 2699179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 2702356SN/A } 2711917SN/A} 2721917SN/A 2731917SN/A 2741917SN/Avoid 2752SN/ABaseCPU::regStats() 2762SN/A{ 277729SN/A using namespace Stats; 278707SN/A 279707SN/A numCycles 280707SN/A .name(name() + ".numCycles") 281707SN/A .desc("number of cpu cycles simulated") 282707SN/A ; 283707SN/A 2847914SBrad.Beckmann@amd.com numWorkItemsStarted 2857914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2867914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 2877914SBrad.Beckmann@amd.com ; 2887914SBrad.Beckmann@amd.com 2897914SBrad.Beckmann@amd.com numWorkItemsCompleted 2907914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 2917914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 2927914SBrad.Beckmann@amd.com ; 2937914SBrad.Beckmann@amd.com 2942680Sktlim@umich.edu int size = threadContexts.size(); 2952SN/A if (size > 1) { 2962SN/A for (int i = 0; i < size; ++i) { 2972SN/A stringstream namestr; 2982SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2992680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 3002SN/A } 3012SN/A } else if (size == 1) 3022680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3032SN/A} 3042SN/A 3059294Sandreas.hansson@arm.comBaseMasterPort & 3069294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 3078850Sandreas.hansson@arm.com{ 3088850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 3098850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 3108850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 3118850Sandreas.hansson@arm.com // return a CpuPort pointer. 3128850Sandreas.hansson@arm.com if (if_name == "dcache_port") 3138922Swilliam.wang@arm.com return getDataPort(); 3148850Sandreas.hansson@arm.com else if (if_name == "icache_port") 3158922Swilliam.wang@arm.com return getInstPort(); 3168850Sandreas.hansson@arm.com else 3178922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 3188850Sandreas.hansson@arm.com} 3198850Sandreas.hansson@arm.com 320180SN/Avoid 3212680Sktlim@umich.eduBaseCPU::registerThreadContexts() 322180SN/A{ 3236221Snate@binkert.org ThreadID size = threadContexts.size(); 3246221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3256221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3262378SN/A 3275718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3285718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3295718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3305718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3315718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3325718Shsul@eecs.umich.edu * I'll just do this for now 3335718Shsul@eecs.umich.edu */ 3346221Snate@binkert.org if (numThreads == 1) 3355718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3365718Shsul@eecs.umich.edu else 3375718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3388779Sgblack@eecs.umich.edu 3398779Sgblack@eecs.umich.edu if (!FullSystem) 3408779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 341180SN/A } 342180SN/A} 343180SN/A 344180SN/A 3454000Ssaidi@eecs.umich.eduint 3464000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3474000Ssaidi@eecs.umich.edu{ 3486221Snate@binkert.org ThreadID size = threadContexts.size(); 3496221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3506221Snate@binkert.org if (tc == threadContexts[tid]) 3516221Snate@binkert.org return tid; 3524000Ssaidi@eecs.umich.edu } 3534000Ssaidi@eecs.umich.edu return 0; 3544000Ssaidi@eecs.umich.edu} 3554000Ssaidi@eecs.umich.edu 356180SN/Avoid 3572798Sktlim@umich.eduBaseCPU::switchOut() 358180SN/A{ 3592359SN/A if (profileEvent && profileEvent->scheduled()) 3605606Snate@binkert.org deschedule(profileEvent); 361180SN/A} 362180SN/A 363180SN/Avoid 3648737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 365180SN/A{ 3662680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 3679152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 3689332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 3699332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 3705712Shsul@eecs.umich.edu 3716221Snate@binkert.org ThreadID size = threadContexts.size(); 3726221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3732680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3742680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 375180SN/A 3762680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3772651Ssaidi@eecs.umich.edu 3782680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3792651Ssaidi@eecs.umich.edu 3805714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 3815715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 3825714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 3832359SN/A 3845875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 3855875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 3865875Ssteve.reinhardt@amd.com * point. 3875875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 3885217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 3895875Ssteve.reinhardt@amd.com */ 3907781SAli.Saidi@ARM.com 3919294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 3929294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 3939294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 3949294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 3957781SAli.Saidi@ARM.com 3967781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 3979178Sandreas.hansson@arm.com if (new_itb_port) { 3989178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 3997781SAli.Saidi@ARM.com assert(old_itb_port); 4009178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 4019294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 4029178Sandreas.hansson@arm.com old_itb_port->unbind(); 4038922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 4047781SAli.Saidi@ARM.com } 4059178Sandreas.hansson@arm.com if (new_dtb_port) { 4069178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 4077781SAli.Saidi@ARM.com assert(old_dtb_port); 4089178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 4099294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 4109178Sandreas.hansson@arm.com old_dtb_port->unbind(); 4118922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 4127781SAli.Saidi@ARM.com } 4138733Sgeoffrey.blake@arm.com 4148887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 4158887Sgeoffrey.blake@arm.com // objects over in the switch 4168887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 4178887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 4188887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 4199294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 4208922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 4219294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 4228922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 4239294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 4248922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 4259294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 4268922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 4278733Sgeoffrey.blake@arm.com 4288887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4299178Sandreas.hansson@arm.com if (new_checker_itb_port) { 4309178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 4318887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4329178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 4339294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4349294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 4359178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 4368922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 4378887Sgeoffrey.blake@arm.com } 4389178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 4399178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 4408887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4419178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 4429294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4439294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 4449178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 4458922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 4468887Sgeoffrey.blake@arm.com } 4478733Sgeoffrey.blake@arm.com } 448180SN/A } 449605SN/A 4503520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4515810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4529152Satgutier@umich.edu oldCPU->interrupts = NULL; 4532254SN/A 4548779Sgblack@eecs.umich.edu if (FullSystem) { 4558779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4568779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4572254SN/A 4588779Sgblack@eecs.umich.edu if (profileEvent) 4598779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4608779Sgblack@eecs.umich.edu } 4614192Sktlim@umich.edu 4629178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 4639178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 4649178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 4659178Sandreas.hansson@arm.com // we are switching to. 4669178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 4679178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 4689294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 4699178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 4709178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 4714192Sktlim@umich.edu 4729178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 4739178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 4749294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 4759178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 4769178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 477180SN/A} 478180SN/A 479180SN/A 4805536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 4815606Snate@binkert.org : cpu(_cpu), interval(_interval) 4821917SN/A{ } 4831917SN/A 4841917SN/Avoid 4851917SN/ABaseCPU::ProfileEvent::process() 4861917SN/A{ 4876221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 4886221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4892680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 4902680Sktlim@umich.edu tc->profileSample(); 4911917SN/A } 4922254SN/A 4937823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 4941917SN/A} 4951917SN/A 4962SN/Avoid 497921SN/ABaseCPU::serialize(std::ostream &os) 498921SN/A{ 4994000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 5009332Sdam.sunwoo@arm.com 5019332Sdam.sunwoo@arm.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 5029332Sdam.sunwoo@arm.com * assigned unique ids that are only meaningful for the duration of 5039332Sdam.sunwoo@arm.com * a specific run. We will need to serialize the entire taskMap in 5049332Sdam.sunwoo@arm.com * system. */ 5059332Sdam.sunwoo@arm.com SERIALIZE_SCALAR(_pid); 5069332Sdam.sunwoo@arm.com 5075647Sgblack@eecs.umich.edu interrupts->serialize(os); 508921SN/A} 509921SN/A 510921SN/Avoid 511921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 512921SN/A{ 5134000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5149332Sdam.sunwoo@arm.com UNSERIALIZE_SCALAR(_pid); 5155647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 516921SN/A} 517921SN/A 5181191SN/Avoid 5191191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5201191SN/A{ 5211191SN/A if (!debugSymbolTable) 5221191SN/A return; 5231191SN/A 5241191SN/A // if pc enters different function, print new function symbol and 5251191SN/A // update saved range. Otherwise do nothing. 5261191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5271191SN/A string sym_str; 5281191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5291191SN/A currentFunctionStart, 5301191SN/A currentFunctionEnd); 5311191SN/A 5321191SN/A if (!found) { 5331191SN/A // no symbol found: use addr as label 5341191SN/A sym_str = csprintf("0x%x", pc); 5351191SN/A currentFunctionStart = pc; 5361191SN/A currentFunctionEnd = pc + 1; 5371191SN/A } 5381191SN/A 5391191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 5407823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 5417823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 5421191SN/A } 5431191SN/A} 5448707Sandreas.hansson@arm.com 5458707Sandreas.hansson@arm.combool 5468975Sandreas.hansson@arm.comBaseCPU::CpuPort::recvTimingResp(PacketPtr pkt) 5478707Sandreas.hansson@arm.com{ 5488948Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvTiming!\n"); 5498707Sandreas.hansson@arm.com return true; 5508707Sandreas.hansson@arm.com} 5518707Sandreas.hansson@arm.com 5528707Sandreas.hansson@arm.comvoid 5538707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRetry() 5548707Sandreas.hansson@arm.com{ 5558948Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvRetry!\n"); 5568707Sandreas.hansson@arm.com} 5578707Sandreas.hansson@arm.com 5588707Sandreas.hansson@arm.comvoid 5598948Sandreas.hansson@arm.comBaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt) 5608707Sandreas.hansson@arm.com{ 5618948Sandreas.hansson@arm.com // No internal storage to update (in the general case). A CPU with 5628948Sandreas.hansson@arm.com // internal storage, e.g. an LSQ that should be part of the 5638948Sandreas.hansson@arm.com // coherent memory has to check against stored data. 5648707Sandreas.hansson@arm.com} 565