base.cc revision 9178
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 561717SN/A#include "cpu/base.hh" 578887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642190SN/A#include "sim/process.hh" 6556SN/A#include "sim/sim_events.hh" 668229Snate@binkert.org#include "sim/sim_exit.hh" 672190SN/A#include "sim/system.hh" 682SN/A 692359SN/A// Hack 702359SN/A#include "sim/stat_control.hh" 712359SN/A 722SN/Ausing namespace std; 732SN/A 742SN/Avector<BaseCPU *> BaseCPU::cpuList; 752SN/A 762SN/A// This variable reflects the max number of threads in any CPU. Be 772SN/A// careful to only use it once all the CPUs that you care about have 782SN/A// been initialized 792SN/Aint maxThreadsPerCPU = 1; 802SN/A 815606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 826144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 836144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 843126Sktlim@umich.edu{ 856144Sksewell@umich.edu if (_interval) 867823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 873126Sktlim@umich.edu} 883126Sktlim@umich.edu 892356SN/Avoid 902356SN/ACPUProgressEvent::process() 912356SN/A{ 928834Satgutier@umich.edu Counter temp = cpu->totalOps(); 932356SN/A#ifndef NDEBUG 946144Sksewell@umich.edu double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 952367SN/A 966144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 976144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 986144Sksewell@umich.edu ipc); 992356SN/A ipc = 0.0; 1002367SN/A#else 1016144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1027823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1036144Sksewell@umich.edu temp - lastNumInst); 1042367SN/A#endif 1052356SN/A lastNumInst = temp; 1066144Sksewell@umich.edu 1076144Sksewell@umich.edu if (_repeatEvent) 1087823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1092356SN/A} 1102356SN/A 1112356SN/Aconst char * 1125336Shines@cs.fsu.eduCPUProgressEvent::description() const 1132356SN/A{ 1144873Sstever@eecs.umich.edu return "CPU Progress"; 1152356SN/A} 1162356SN/A 1178876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 1189157Sandreas.hansson@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 1198832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1208832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1215712Shsul@eecs.umich.edu interrupts(p->interrupts), 1229157Sandreas.hansson@arm.com numThreads(p->numThreads), system(p->system) 1232SN/A{ 1245712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1255712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1265712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1275712Shsul@eecs.umich.edu } 1285712Shsul@eecs.umich.edu 1292SN/A // add self to global list of CPUs 1302SN/A cpuList.push_back(this); 1312SN/A 1325712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1335712Shsul@eecs.umich.edu 1346221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1356221Snate@binkert.org maxThreadsPerCPU = numThreads; 1362SN/A 1372SN/A // allocate per-thread instruction-based event queues 1386221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1406221Snate@binkert.org comInstEventQueue[tid] = 1416221Snate@binkert.org new EventQueue("instruction-based event queue"); 1422SN/A 1432SN/A // 1442SN/A // set up instruction-count-based termination events, if any 1452SN/A // 1465606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1475606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1486221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1495606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1506221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1515606Snate@binkert.org } 1525606Snate@binkert.org } 1532SN/A 1541400SN/A if (p->max_insts_all_threads != 0) { 1555606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1565606Snate@binkert.org 1572SN/A // allocate & initialize shared downcounter: each event will 1582SN/A // decrement this when triggered; simulation will terminate 1592SN/A // when counter reaches 0 1602SN/A int *counter = new int; 1616221Snate@binkert.org *counter = numThreads; 1626221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1635606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1646670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1655606Snate@binkert.org } 1662SN/A } 1672SN/A 168124SN/A // allocate per-thread load-based event queues 1696221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1706221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1716221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 172124SN/A 173124SN/A // 174124SN/A // set up instruction-count-based termination events, if any 175124SN/A // 1765606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1775606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1786221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1795606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1806221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1815606Snate@binkert.org } 1825606Snate@binkert.org } 183124SN/A 1841400SN/A if (p->max_loads_all_threads != 0) { 1855606Snate@binkert.org const char *cause = "all threads reached the max load count"; 186124SN/A // allocate & initialize shared downcounter: each event will 187124SN/A // decrement this when triggered; simulation will terminate 188124SN/A // when counter reaches 0 189124SN/A int *counter = new int; 1906221Snate@binkert.org *counter = numThreads; 1916221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1925606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1936221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 1945606Snate@binkert.org } 195124SN/A } 196124SN/A 1971191SN/A functionTracingEnabled = false; 1985529Snate@binkert.org if (p->function_trace) { 1998634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2008634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2018634Schris.emmons@arm.com if (!functionTraceStream) 2028634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2038634Schris.emmons@arm.com 2041191SN/A currentFunctionStart = currentFunctionEnd = 0; 2055529Snate@binkert.org functionEntryTick = p->function_trace_start; 2061191SN/A 2075529Snate@binkert.org if (p->function_trace_start == 0) { 2081191SN/A functionTracingEnabled = true; 2091191SN/A } else { 2105606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2115606Snate@binkert.org Event *event = new wrap(this, true); 2125606Snate@binkert.org schedule(event, p->function_trace_start); 2131191SN/A } 2141191SN/A } 2158876Sandreas.hansson@arm.com 2168876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2178876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2188876Sandreas.hansson@arm.com if (!params()->defer_registration && !is_checker) { 2198876Sandreas.hansson@arm.com if (interrupts) { 2208876Sandreas.hansson@arm.com interrupts->setCPU(this); 2218876Sandreas.hansson@arm.com } else { 2228876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2238876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2248876Sandreas.hansson@arm.com } 2258876Sandreas.hansson@arm.com } 2265810Sgblack@eecs.umich.edu 2278779Sgblack@eecs.umich.edu if (FullSystem) { 2288779Sgblack@eecs.umich.edu profileEvent = NULL; 2298779Sgblack@eecs.umich.edu if (params()->profile) 2308779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2318779Sgblack@eecs.umich.edu } 2325529Snate@binkert.org tracer = params()->tracer; 2331917SN/A} 2341191SN/A 2351191SN/Avoid 2361191SN/ABaseCPU::enableFunctionTrace() 2371191SN/A{ 2381191SN/A functionTracingEnabled = true; 2391191SN/A} 2401191SN/A 2411191SN/ABaseCPU::~BaseCPU() 2421191SN/A{ 2439086Sandreas.hansson@arm.com delete profileEvent; 2449086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2459086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2461191SN/A} 2471191SN/A 2481129SN/Avoid 2491129SN/ABaseCPU::init() 2501129SN/A{ 2515529Snate@binkert.org if (!params()->defer_registration) 2522680Sktlim@umich.edu registerThreadContexts(); 2531129SN/A} 254180SN/A 2552SN/Avoid 2561917SN/ABaseCPU::startup() 2571917SN/A{ 2588779Sgblack@eecs.umich.edu if (FullSystem) { 2598779Sgblack@eecs.umich.edu if (!params()->defer_registration && profileEvent) 2608779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2618779Sgblack@eecs.umich.edu } 2622356SN/A 2635529Snate@binkert.org if (params()->progress_interval) { 2645606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2656144Sksewell@umich.edu 2668607Sgblack@eecs.umich.edu new CPUProgressEvent(this, num_ticks); 2672356SN/A } 2681917SN/A} 2691917SN/A 2701917SN/A 2711917SN/Avoid 2722SN/ABaseCPU::regStats() 2732SN/A{ 274729SN/A using namespace Stats; 275707SN/A 276707SN/A numCycles 277707SN/A .name(name() + ".numCycles") 278707SN/A .desc("number of cpu cycles simulated") 279707SN/A ; 280707SN/A 2817914SBrad.Beckmann@amd.com numWorkItemsStarted 2827914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2837914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 2847914SBrad.Beckmann@amd.com ; 2857914SBrad.Beckmann@amd.com 2867914SBrad.Beckmann@amd.com numWorkItemsCompleted 2877914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 2887914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 2897914SBrad.Beckmann@amd.com ; 2907914SBrad.Beckmann@amd.com 2912680Sktlim@umich.edu int size = threadContexts.size(); 2922SN/A if (size > 1) { 2932SN/A for (int i = 0; i < size; ++i) { 2942SN/A stringstream namestr; 2952SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2962680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2972SN/A } 2982SN/A } else if (size == 1) 2992680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3002SN/A} 3012SN/A 3028922Swilliam.wang@arm.comMasterPort & 3038922Swilliam.wang@arm.comBaseCPU::getMasterPort(const string &if_name, int idx) 3048850Sandreas.hansson@arm.com{ 3058850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 3068850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 3078850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 3088850Sandreas.hansson@arm.com // return a CpuPort pointer. 3098850Sandreas.hansson@arm.com if (if_name == "dcache_port") 3108922Swilliam.wang@arm.com return getDataPort(); 3118850Sandreas.hansson@arm.com else if (if_name == "icache_port") 3128922Swilliam.wang@arm.com return getInstPort(); 3138850Sandreas.hansson@arm.com else 3148922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 3158850Sandreas.hansson@arm.com} 3168850Sandreas.hansson@arm.com 317180SN/Avoid 3182680Sktlim@umich.eduBaseCPU::registerThreadContexts() 319180SN/A{ 3206221Snate@binkert.org ThreadID size = threadContexts.size(); 3216221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3226221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3232378SN/A 3245718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3255718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3265718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3275718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3285718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3295718Shsul@eecs.umich.edu * I'll just do this for now 3305718Shsul@eecs.umich.edu */ 3316221Snate@binkert.org if (numThreads == 1) 3325718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3335718Shsul@eecs.umich.edu else 3345718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3358779Sgblack@eecs.umich.edu 3368779Sgblack@eecs.umich.edu if (!FullSystem) 3378779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 338180SN/A } 339180SN/A} 340180SN/A 341180SN/A 3424000Ssaidi@eecs.umich.eduint 3434000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3444000Ssaidi@eecs.umich.edu{ 3456221Snate@binkert.org ThreadID size = threadContexts.size(); 3466221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3476221Snate@binkert.org if (tc == threadContexts[tid]) 3486221Snate@binkert.org return tid; 3494000Ssaidi@eecs.umich.edu } 3504000Ssaidi@eecs.umich.edu return 0; 3514000Ssaidi@eecs.umich.edu} 3524000Ssaidi@eecs.umich.edu 353180SN/Avoid 3542798Sktlim@umich.eduBaseCPU::switchOut() 355180SN/A{ 3562359SN/A if (profileEvent && profileEvent->scheduled()) 3575606Snate@binkert.org deschedule(profileEvent); 358180SN/A} 359180SN/A 360180SN/Avoid 3618737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 362180SN/A{ 3632680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 3649152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 3655712Shsul@eecs.umich.edu 3666221Snate@binkert.org ThreadID size = threadContexts.size(); 3676221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3682680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3692680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 370180SN/A 3712680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3722651Ssaidi@eecs.umich.edu 3732680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3742651Ssaidi@eecs.umich.edu 3755714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 3765715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 3775714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 3782359SN/A 3795875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 3805875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 3815875Ssteve.reinhardt@amd.com * point. 3825875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 3835217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 3845875Ssteve.reinhardt@amd.com */ 3857781SAli.Saidi@ARM.com 3868922Swilliam.wang@arm.com MasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 3878922Swilliam.wang@arm.com MasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 3888922Swilliam.wang@arm.com MasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 3898922Swilliam.wang@arm.com MasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 3907781SAli.Saidi@ARM.com 3917781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 3929178Sandreas.hansson@arm.com if (new_itb_port) { 3939178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 3947781SAli.Saidi@ARM.com assert(old_itb_port); 3959178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 3968922Swilliam.wang@arm.com SlavePort &slavePort = old_itb_port->getSlavePort(); 3979178Sandreas.hansson@arm.com old_itb_port->unbind(); 3988922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 3997781SAli.Saidi@ARM.com } 4009178Sandreas.hansson@arm.com if (new_dtb_port) { 4019178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 4027781SAli.Saidi@ARM.com assert(old_dtb_port); 4039178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 4048922Swilliam.wang@arm.com SlavePort &slavePort = old_dtb_port->getSlavePort(); 4059178Sandreas.hansson@arm.com old_dtb_port->unbind(); 4068922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 4077781SAli.Saidi@ARM.com } 4088733Sgeoffrey.blake@arm.com 4098887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 4108887Sgeoffrey.blake@arm.com // objects over in the switch 4118887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 4128887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 4138887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 4148922Swilliam.wang@arm.com MasterPort *old_checker_itb_port = 4158922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 4168922Swilliam.wang@arm.com MasterPort *old_checker_dtb_port = 4178922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 4188922Swilliam.wang@arm.com MasterPort *new_checker_itb_port = 4198922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 4208922Swilliam.wang@arm.com MasterPort *new_checker_dtb_port = 4218922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 4228733Sgeoffrey.blake@arm.com 4238887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4249178Sandreas.hansson@arm.com if (new_checker_itb_port) { 4259178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 4268887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4279178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 4289178Sandreas.hansson@arm.com SlavePort &slavePort = old_checker_itb_port->getSlavePort(); 4299178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 4308922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 4318887Sgeoffrey.blake@arm.com } 4329178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 4339178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 4348887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4359178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 4369178Sandreas.hansson@arm.com SlavePort &slavePort = old_checker_dtb_port->getSlavePort(); 4379178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 4388922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 4398887Sgeoffrey.blake@arm.com } 4408733Sgeoffrey.blake@arm.com } 441180SN/A } 442605SN/A 4433520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4445810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4459152Satgutier@umich.edu oldCPU->interrupts = NULL; 4462254SN/A 4478779Sgblack@eecs.umich.edu if (FullSystem) { 4488779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4498779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4502254SN/A 4518779Sgblack@eecs.umich.edu if (profileEvent) 4528779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4538779Sgblack@eecs.umich.edu } 4544192Sktlim@umich.edu 4559178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 4569178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 4579178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 4589178Sandreas.hansson@arm.com // we are switching to. 4599178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 4609178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 4619178Sandreas.hansson@arm.com SlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 4629178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 4639178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 4644192Sktlim@umich.edu 4659178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 4669178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 4679178Sandreas.hansson@arm.com SlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 4689178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 4699178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 470180SN/A} 471180SN/A 472180SN/A 4735536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 4745606Snate@binkert.org : cpu(_cpu), interval(_interval) 4751917SN/A{ } 4761917SN/A 4771917SN/Avoid 4781917SN/ABaseCPU::ProfileEvent::process() 4791917SN/A{ 4806221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 4816221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4822680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 4832680Sktlim@umich.edu tc->profileSample(); 4841917SN/A } 4852254SN/A 4867823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 4871917SN/A} 4881917SN/A 4892SN/Avoid 490921SN/ABaseCPU::serialize(std::ostream &os) 491921SN/A{ 4924000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 4935647Sgblack@eecs.umich.edu interrupts->serialize(os); 494921SN/A} 495921SN/A 496921SN/Avoid 497921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 498921SN/A{ 4994000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5005647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 501921SN/A} 502921SN/A 5031191SN/Avoid 5041191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5051191SN/A{ 5061191SN/A if (!debugSymbolTable) 5071191SN/A return; 5081191SN/A 5091191SN/A // if pc enters different function, print new function symbol and 5101191SN/A // update saved range. Otherwise do nothing. 5111191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5121191SN/A string sym_str; 5131191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5141191SN/A currentFunctionStart, 5151191SN/A currentFunctionEnd); 5161191SN/A 5171191SN/A if (!found) { 5181191SN/A // no symbol found: use addr as label 5191191SN/A sym_str = csprintf("0x%x", pc); 5201191SN/A currentFunctionStart = pc; 5211191SN/A currentFunctionEnd = pc + 1; 5221191SN/A } 5231191SN/A 5241191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 5257823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 5267823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 5271191SN/A } 5281191SN/A} 5298707Sandreas.hansson@arm.com 5308707Sandreas.hansson@arm.combool 5318975Sandreas.hansson@arm.comBaseCPU::CpuPort::recvTimingResp(PacketPtr pkt) 5328707Sandreas.hansson@arm.com{ 5338948Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvTiming!\n"); 5348707Sandreas.hansson@arm.com return true; 5358707Sandreas.hansson@arm.com} 5368707Sandreas.hansson@arm.com 5378707Sandreas.hansson@arm.comvoid 5388707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRetry() 5398707Sandreas.hansson@arm.com{ 5408948Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvRetry!\n"); 5418707Sandreas.hansson@arm.com} 5428707Sandreas.hansson@arm.com 5438707Sandreas.hansson@arm.comvoid 5448948Sandreas.hansson@arm.comBaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt) 5458707Sandreas.hansson@arm.com{ 5468948Sandreas.hansson@arm.com // No internal storage to update (in the general case). A CPU with 5478948Sandreas.hansson@arm.com // internal storage, e.g. an LSQ that should be part of the 5488948Sandreas.hansson@arm.com // coherent memory has to check against stored data. 5498707Sandreas.hansson@arm.com} 550