base.cc revision 8887
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 561717SN/A#include "cpu/base.hh" 578887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642190SN/A#include "sim/process.hh" 6556SN/A#include "sim/sim_events.hh" 668229Snate@binkert.org#include "sim/sim_exit.hh" 672190SN/A#include "sim/system.hh" 682SN/A 692359SN/A// Hack 702359SN/A#include "sim/stat_control.hh" 712359SN/A 722SN/Ausing namespace std; 732SN/A 742SN/Avector<BaseCPU *> BaseCPU::cpuList; 752SN/A 762SN/A// This variable reflects the max number of threads in any CPU. Be 772SN/A// careful to only use it once all the CPUs that you care about have 782SN/A// been initialized 792SN/Aint maxThreadsPerCPU = 1; 802SN/A 815606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 826144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 836144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 843126Sktlim@umich.edu{ 856144Sksewell@umich.edu if (_interval) 867823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 873126Sktlim@umich.edu} 883126Sktlim@umich.edu 892356SN/Avoid 902356SN/ACPUProgressEvent::process() 912356SN/A{ 928834Satgutier@umich.edu Counter temp = cpu->totalOps(); 932356SN/A#ifndef NDEBUG 946144Sksewell@umich.edu double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 952367SN/A 966144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 976144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 986144Sksewell@umich.edu ipc); 992356SN/A ipc = 0.0; 1002367SN/A#else 1016144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1027823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1036144Sksewell@umich.edu temp - lastNumInst); 1042367SN/A#endif 1052356SN/A lastNumInst = temp; 1066144Sksewell@umich.edu 1076144Sksewell@umich.edu if (_repeatEvent) 1087823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1092356SN/A} 1102356SN/A 1112356SN/Aconst char * 1125336Shines@cs.fsu.eduCPUProgressEvent::description() const 1132356SN/A{ 1144873Sstever@eecs.umich.edu return "CPU Progress"; 1152356SN/A} 1162356SN/A 1178876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 1185712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 1198832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1208832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1215712Shsul@eecs.umich.edu interrupts(p->interrupts), 1226221Snate@binkert.org numThreads(p->numThreads), system(p->system), 1233661Srdreslin@umich.edu phase(p->phase) 1242SN/A{ 1257823Ssteve.reinhardt@amd.com// currentTick = curTick(); 1261062SN/A 1275712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1285712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1295712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1305712Shsul@eecs.umich.edu } 1315712Shsul@eecs.umich.edu 1322SN/A // add self to global list of CPUs 1332SN/A cpuList.push_back(this); 1342SN/A 1355712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1365712Shsul@eecs.umich.edu 1376221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1386221Snate@binkert.org maxThreadsPerCPU = numThreads; 1392SN/A 1402SN/A // allocate per-thread instruction-based event queues 1416221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1426221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1436221Snate@binkert.org comInstEventQueue[tid] = 1446221Snate@binkert.org new EventQueue("instruction-based event queue"); 1452SN/A 1462SN/A // 1472SN/A // set up instruction-count-based termination events, if any 1482SN/A // 1495606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1505606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1516221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1525606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1536221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1545606Snate@binkert.org } 1555606Snate@binkert.org } 1562SN/A 1571400SN/A if (p->max_insts_all_threads != 0) { 1585606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1595606Snate@binkert.org 1602SN/A // allocate & initialize shared downcounter: each event will 1612SN/A // decrement this when triggered; simulation will terminate 1622SN/A // when counter reaches 0 1632SN/A int *counter = new int; 1646221Snate@binkert.org *counter = numThreads; 1656221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1665606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1676670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1685606Snate@binkert.org } 1692SN/A } 1702SN/A 171124SN/A // allocate per-thread load-based event queues 1726221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1736221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1746221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 175124SN/A 176124SN/A // 177124SN/A // set up instruction-count-based termination events, if any 178124SN/A // 1795606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1805606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1816221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1825606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1836221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1845606Snate@binkert.org } 1855606Snate@binkert.org } 186124SN/A 1871400SN/A if (p->max_loads_all_threads != 0) { 1885606Snate@binkert.org const char *cause = "all threads reached the max load count"; 189124SN/A // allocate & initialize shared downcounter: each event will 190124SN/A // decrement this when triggered; simulation will terminate 191124SN/A // when counter reaches 0 192124SN/A int *counter = new int; 1936221Snate@binkert.org *counter = numThreads; 1946221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1955606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1966221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 1975606Snate@binkert.org } 198124SN/A } 199124SN/A 2001191SN/A functionTracingEnabled = false; 2015529Snate@binkert.org if (p->function_trace) { 2028634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2038634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2048634Schris.emmons@arm.com if (!functionTraceStream) 2058634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2068634Schris.emmons@arm.com 2071191SN/A currentFunctionStart = currentFunctionEnd = 0; 2085529Snate@binkert.org functionEntryTick = p->function_trace_start; 2091191SN/A 2105529Snate@binkert.org if (p->function_trace_start == 0) { 2111191SN/A functionTracingEnabled = true; 2121191SN/A } else { 2135606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2145606Snate@binkert.org Event *event = new wrap(this, true); 2155606Snate@binkert.org schedule(event, p->function_trace_start); 2161191SN/A } 2171191SN/A } 2188876Sandreas.hansson@arm.com 2198876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2208876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2218876Sandreas.hansson@arm.com if (!params()->defer_registration && !is_checker) { 2228876Sandreas.hansson@arm.com if (interrupts) { 2238876Sandreas.hansson@arm.com interrupts->setCPU(this); 2248876Sandreas.hansson@arm.com } else { 2258876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2268876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2278876Sandreas.hansson@arm.com } 2288876Sandreas.hansson@arm.com } 2295810Sgblack@eecs.umich.edu 2308779Sgblack@eecs.umich.edu if (FullSystem) { 2318779Sgblack@eecs.umich.edu profileEvent = NULL; 2328779Sgblack@eecs.umich.edu if (params()->profile) 2338779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2348779Sgblack@eecs.umich.edu } 2355529Snate@binkert.org tracer = params()->tracer; 2361917SN/A} 2371191SN/A 2381191SN/Avoid 2391191SN/ABaseCPU::enableFunctionTrace() 2401191SN/A{ 2411191SN/A functionTracingEnabled = true; 2421191SN/A} 2431191SN/A 2441191SN/ABaseCPU::~BaseCPU() 2451191SN/A{ 2461191SN/A} 2471191SN/A 2481129SN/Avoid 2491129SN/ABaseCPU::init() 2501129SN/A{ 2515529Snate@binkert.org if (!params()->defer_registration) 2522680Sktlim@umich.edu registerThreadContexts(); 2531129SN/A} 254180SN/A 2552SN/Avoid 2561917SN/ABaseCPU::startup() 2571917SN/A{ 2588779Sgblack@eecs.umich.edu if (FullSystem) { 2598779Sgblack@eecs.umich.edu if (!params()->defer_registration && profileEvent) 2608779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2618779Sgblack@eecs.umich.edu } 2622356SN/A 2635529Snate@binkert.org if (params()->progress_interval) { 2645606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2656144Sksewell@umich.edu 2668607Sgblack@eecs.umich.edu new CPUProgressEvent(this, num_ticks); 2672356SN/A } 2681917SN/A} 2691917SN/A 2701917SN/A 2711917SN/Avoid 2722SN/ABaseCPU::regStats() 2732SN/A{ 274729SN/A using namespace Stats; 275707SN/A 276707SN/A numCycles 277707SN/A .name(name() + ".numCycles") 278707SN/A .desc("number of cpu cycles simulated") 279707SN/A ; 280707SN/A 2817914SBrad.Beckmann@amd.com numWorkItemsStarted 2827914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2837914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 2847914SBrad.Beckmann@amd.com ; 2857914SBrad.Beckmann@amd.com 2867914SBrad.Beckmann@amd.com numWorkItemsCompleted 2877914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 2887914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 2897914SBrad.Beckmann@amd.com ; 2907914SBrad.Beckmann@amd.com 2912680Sktlim@umich.edu int size = threadContexts.size(); 2922SN/A if (size > 1) { 2932SN/A for (int i = 0; i < size; ++i) { 2942SN/A stringstream namestr; 2952SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2962680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2972SN/A } 2982SN/A } else if (size == 1) 2992680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3002SN/A} 3012SN/A 3028850Sandreas.hansson@arm.comPort * 3038850Sandreas.hansson@arm.comBaseCPU::getPort(const string &if_name, int idx) 3048850Sandreas.hansson@arm.com{ 3058850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 3068850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 3078850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 3088850Sandreas.hansson@arm.com // return a CpuPort pointer. 3098850Sandreas.hansson@arm.com if (if_name == "dcache_port") 3108850Sandreas.hansson@arm.com return &getDataPort(); 3118850Sandreas.hansson@arm.com else if (if_name == "icache_port") 3128850Sandreas.hansson@arm.com return &getInstPort(); 3138850Sandreas.hansson@arm.com else 3148850Sandreas.hansson@arm.com panic("CPU %s has no port named %s\n", name(), if_name); 3158850Sandreas.hansson@arm.com} 3168850Sandreas.hansson@arm.com 3173495Sktlim@umich.eduTick 3183495Sktlim@umich.eduBaseCPU::nextCycle() 3193495Sktlim@umich.edu{ 3207823Ssteve.reinhardt@amd.com Tick next_tick = curTick() - phase + clock - 1; 3213495Sktlim@umich.edu next_tick -= (next_tick % clock); 3223661Srdreslin@umich.edu next_tick += phase; 3233495Sktlim@umich.edu return next_tick; 3243495Sktlim@umich.edu} 3253495Sktlim@umich.edu 3263495Sktlim@umich.eduTick 3273495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 3283495Sktlim@umich.edu{ 3293495Sktlim@umich.edu Tick next_tick = begin_tick; 3304599Sacolyte@umich.edu if (next_tick % clock != 0) 3314599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 3323661Srdreslin@umich.edu next_tick += phase; 3333495Sktlim@umich.edu 3347823Ssteve.reinhardt@amd.com assert(next_tick >= curTick()); 3353495Sktlim@umich.edu return next_tick; 3363495Sktlim@umich.edu} 337180SN/A 338180SN/Avoid 3392680Sktlim@umich.eduBaseCPU::registerThreadContexts() 340180SN/A{ 3416221Snate@binkert.org ThreadID size = threadContexts.size(); 3426221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3436221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3442378SN/A 3455718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3465718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3475718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3485718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3495718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3505718Shsul@eecs.umich.edu * I'll just do this for now 3515718Shsul@eecs.umich.edu */ 3526221Snate@binkert.org if (numThreads == 1) 3535718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3545718Shsul@eecs.umich.edu else 3555718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3568779Sgblack@eecs.umich.edu 3578779Sgblack@eecs.umich.edu if (!FullSystem) 3588779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 359180SN/A } 360180SN/A} 361180SN/A 362180SN/A 3634000Ssaidi@eecs.umich.eduint 3644000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3654000Ssaidi@eecs.umich.edu{ 3666221Snate@binkert.org ThreadID size = threadContexts.size(); 3676221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3686221Snate@binkert.org if (tc == threadContexts[tid]) 3696221Snate@binkert.org return tid; 3704000Ssaidi@eecs.umich.edu } 3714000Ssaidi@eecs.umich.edu return 0; 3724000Ssaidi@eecs.umich.edu} 3734000Ssaidi@eecs.umich.edu 374180SN/Avoid 3752798Sktlim@umich.eduBaseCPU::switchOut() 376180SN/A{ 3772359SN/A if (profileEvent && profileEvent->scheduled()) 3785606Snate@binkert.org deschedule(profileEvent); 379180SN/A} 380180SN/A 381180SN/Avoid 3828737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 383180SN/A{ 3848850Sandreas.hansson@arm.com CpuPort &ic = getInstPort(); 3858850Sandreas.hansson@arm.com CpuPort &dc = getDataPort(); 3862680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 387180SN/A 3885712Shsul@eecs.umich.edu _cpuId = oldCPU->cpuId(); 3895712Shsul@eecs.umich.edu 3906221Snate@binkert.org ThreadID size = threadContexts.size(); 3916221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3922680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3932680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 394180SN/A 3952680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3962651Ssaidi@eecs.umich.edu 3972680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3982651Ssaidi@eecs.umich.edu 3995714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 4005715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 4015714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 4022359SN/A 4035875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 4045875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 4055875Ssteve.reinhardt@amd.com * point. 4065875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 4075217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 4085875Ssteve.reinhardt@amd.com */ 4097781SAli.Saidi@ARM.com 4107781SAli.Saidi@ARM.com Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; 4117781SAli.Saidi@ARM.com old_itb_port = oldTC->getITBPtr()->getPort(); 4127781SAli.Saidi@ARM.com old_dtb_port = oldTC->getDTBPtr()->getPort(); 4137781SAli.Saidi@ARM.com new_itb_port = newTC->getITBPtr()->getPort(); 4147781SAli.Saidi@ARM.com new_dtb_port = newTC->getDTBPtr()->getPort(); 4157781SAli.Saidi@ARM.com 4167781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 4177781SAli.Saidi@ARM.com if (new_itb_port && !new_itb_port->isConnected()) { 4187781SAli.Saidi@ARM.com assert(old_itb_port); 4197781SAli.Saidi@ARM.com Port *peer = old_itb_port->getPeer();; 4207781SAli.Saidi@ARM.com new_itb_port->setPeer(peer); 4217781SAli.Saidi@ARM.com peer->setPeer(new_itb_port); 4227781SAli.Saidi@ARM.com } 4237781SAli.Saidi@ARM.com if (new_dtb_port && !new_dtb_port->isConnected()) { 4247781SAli.Saidi@ARM.com assert(old_dtb_port); 4257781SAli.Saidi@ARM.com Port *peer = old_dtb_port->getPeer();; 4267781SAli.Saidi@ARM.com new_dtb_port->setPeer(peer); 4277781SAli.Saidi@ARM.com peer->setPeer(new_dtb_port); 4287781SAli.Saidi@ARM.com } 4298733Sgeoffrey.blake@arm.com 4308887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 4318887Sgeoffrey.blake@arm.com // objects over in the switch 4328887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 4338887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 4348887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 4358887Sgeoffrey.blake@arm.com Port *old_checker_itb_port, *old_checker_dtb_port; 4368887Sgeoffrey.blake@arm.com Port *new_checker_itb_port, *new_checker_dtb_port; 4378733Sgeoffrey.blake@arm.com 4388887Sgeoffrey.blake@arm.com old_checker_itb_port = oldChecker->getITBPtr()->getPort(); 4398887Sgeoffrey.blake@arm.com old_checker_dtb_port = oldChecker->getDTBPtr()->getPort(); 4408887Sgeoffrey.blake@arm.com new_checker_itb_port = newChecker->getITBPtr()->getPort(); 4418887Sgeoffrey.blake@arm.com new_checker_dtb_port = newChecker->getDTBPtr()->getPort(); 4428733Sgeoffrey.blake@arm.com 4438887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4448887Sgeoffrey.blake@arm.com if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { 4458887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4468887Sgeoffrey.blake@arm.com Port *peer = old_checker_itb_port->getPeer();; 4478887Sgeoffrey.blake@arm.com new_checker_itb_port->setPeer(peer); 4488887Sgeoffrey.blake@arm.com peer->setPeer(new_checker_itb_port); 4498887Sgeoffrey.blake@arm.com } 4508887Sgeoffrey.blake@arm.com if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { 4518887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4528887Sgeoffrey.blake@arm.com Port *peer = old_checker_dtb_port->getPeer();; 4538887Sgeoffrey.blake@arm.com new_checker_dtb_port->setPeer(peer); 4548887Sgeoffrey.blake@arm.com peer->setPeer(new_checker_dtb_port); 4558887Sgeoffrey.blake@arm.com } 4568733Sgeoffrey.blake@arm.com } 457180SN/A } 458605SN/A 4593520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4605810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4612254SN/A 4628779Sgblack@eecs.umich.edu if (FullSystem) { 4638779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4648779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4652254SN/A 4668779Sgblack@eecs.umich.edu if (profileEvent) 4678779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4688779Sgblack@eecs.umich.edu } 4694192Sktlim@umich.edu 4704192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 4714192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 4724192Sktlim@umich.edu // CPU. 4738850Sandreas.hansson@arm.com if (!ic.isConnected()) { 4748850Sandreas.hansson@arm.com Port *peer = oldCPU->getInstPort().getPeer(); 4758850Sandreas.hansson@arm.com ic.setPeer(peer); 4768850Sandreas.hansson@arm.com peer->setPeer(&ic); 4774192Sktlim@umich.edu } 4784192Sktlim@umich.edu 4798850Sandreas.hansson@arm.com if (!dc.isConnected()) { 4808850Sandreas.hansson@arm.com Port *peer = oldCPU->getDataPort().getPeer(); 4818850Sandreas.hansson@arm.com dc.setPeer(peer); 4828850Sandreas.hansson@arm.com peer->setPeer(&dc); 4834192Sktlim@umich.edu } 484180SN/A} 485180SN/A 486180SN/A 4875536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 4885606Snate@binkert.org : cpu(_cpu), interval(_interval) 4891917SN/A{ } 4901917SN/A 4911917SN/Avoid 4921917SN/ABaseCPU::ProfileEvent::process() 4931917SN/A{ 4946221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 4956221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4962680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 4972680Sktlim@umich.edu tc->profileSample(); 4981917SN/A } 4992254SN/A 5007823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 5011917SN/A} 5021917SN/A 5032SN/Avoid 504921SN/ABaseCPU::serialize(std::ostream &os) 505921SN/A{ 5064000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 5075647Sgblack@eecs.umich.edu interrupts->serialize(os); 508921SN/A} 509921SN/A 510921SN/Avoid 511921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 512921SN/A{ 5134000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5145647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 515921SN/A} 516921SN/A 5171191SN/Avoid 5181191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5191191SN/A{ 5201191SN/A if (!debugSymbolTable) 5211191SN/A return; 5221191SN/A 5231191SN/A // if pc enters different function, print new function symbol and 5241191SN/A // update saved range. Otherwise do nothing. 5251191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5261191SN/A string sym_str; 5271191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5281191SN/A currentFunctionStart, 5291191SN/A currentFunctionEnd); 5301191SN/A 5311191SN/A if (!found) { 5321191SN/A // no symbol found: use addr as label 5331191SN/A sym_str = csprintf("0x%x", pc); 5341191SN/A currentFunctionStart = pc; 5351191SN/A currentFunctionEnd = pc + 1; 5361191SN/A } 5371191SN/A 5381191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 5397823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 5407823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 5411191SN/A } 5421191SN/A} 5438707Sandreas.hansson@arm.com 5448707Sandreas.hansson@arm.combool 5458707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvTiming(PacketPtr pkt) 5468707Sandreas.hansson@arm.com{ 5478707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvTiming callback!"); 5488707Sandreas.hansson@arm.com return true; 5498707Sandreas.hansson@arm.com} 5508707Sandreas.hansson@arm.com 5518707Sandreas.hansson@arm.comvoid 5528707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRetry() 5538707Sandreas.hansson@arm.com{ 5548707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvRetry callback!"); 5558707Sandreas.hansson@arm.com} 5568707Sandreas.hansson@arm.com 5578707Sandreas.hansson@arm.comTick 5588707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvAtomic(PacketPtr pkt) 5598707Sandreas.hansson@arm.com{ 5608707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvAtomic callback!"); 5618707Sandreas.hansson@arm.com return curTick(); 5628707Sandreas.hansson@arm.com} 5638707Sandreas.hansson@arm.com 5648707Sandreas.hansson@arm.comvoid 5658707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvFunctional(PacketPtr pkt) 5668707Sandreas.hansson@arm.com{ 5678707Sandreas.hansson@arm.com // No internal storage to update (in the general case). In the 5688707Sandreas.hansson@arm.com // long term this should never be called, but that assumed a split 5698707Sandreas.hansson@arm.com // into master/slave and request/response. 5708707Sandreas.hansson@arm.com} 5718707Sandreas.hansson@arm.com 5728707Sandreas.hansson@arm.comvoid 5738711Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRangeChange() 5748707Sandreas.hansson@arm.com{ 5758707Sandreas.hansson@arm.com} 576