base.cc revision 8876
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 568733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 571717SN/A#include "cpu/base.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642190SN/A#include "sim/process.hh" 6556SN/A#include "sim/sim_events.hh" 668229Snate@binkert.org#include "sim/sim_exit.hh" 672190SN/A#include "sim/system.hh" 682SN/A 698733Sgeoffrey.blake@arm.com#if USE_CHECKER 708733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 718733Sgeoffrey.blake@arm.com#endif 728733Sgeoffrey.blake@arm.com 732359SN/A// Hack 742359SN/A#include "sim/stat_control.hh" 752359SN/A 762SN/Ausing namespace std; 772SN/A 782SN/Avector<BaseCPU *> BaseCPU::cpuList; 792SN/A 802SN/A// This variable reflects the max number of threads in any CPU. Be 812SN/A// careful to only use it once all the CPUs that you care about have 822SN/A// been initialized 832SN/Aint maxThreadsPerCPU = 1; 842SN/A 855606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 866144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 876144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 883126Sktlim@umich.edu{ 896144Sksewell@umich.edu if (_interval) 907823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 913126Sktlim@umich.edu} 923126Sktlim@umich.edu 932356SN/Avoid 942356SN/ACPUProgressEvent::process() 952356SN/A{ 968834Satgutier@umich.edu Counter temp = cpu->totalOps(); 972356SN/A#ifndef NDEBUG 986144Sksewell@umich.edu double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 992367SN/A 1006144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1016144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1026144Sksewell@umich.edu ipc); 1032356SN/A ipc = 0.0; 1042367SN/A#else 1056144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1067823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1076144Sksewell@umich.edu temp - lastNumInst); 1082367SN/A#endif 1092356SN/A lastNumInst = temp; 1106144Sksewell@umich.edu 1116144Sksewell@umich.edu if (_repeatEvent) 1127823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1132356SN/A} 1142356SN/A 1152356SN/Aconst char * 1165336Shines@cs.fsu.eduCPUProgressEvent::description() const 1172356SN/A{ 1184873Sstever@eecs.umich.edu return "CPU Progress"; 1192356SN/A} 1202356SN/A 1218876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 1225712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 1238832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1248832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1255712Shsul@eecs.umich.edu interrupts(p->interrupts), 1266221Snate@binkert.org numThreads(p->numThreads), system(p->system), 1273661Srdreslin@umich.edu phase(p->phase) 1282SN/A{ 1297823Ssteve.reinhardt@amd.com// currentTick = curTick(); 1301062SN/A 1315712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1325712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1335712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1345712Shsul@eecs.umich.edu } 1355712Shsul@eecs.umich.edu 1362SN/A // add self to global list of CPUs 1372SN/A cpuList.push_back(this); 1382SN/A 1395712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1405712Shsul@eecs.umich.edu 1416221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1426221Snate@binkert.org maxThreadsPerCPU = numThreads; 1432SN/A 1442SN/A // allocate per-thread instruction-based event queues 1456221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1466221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1476221Snate@binkert.org comInstEventQueue[tid] = 1486221Snate@binkert.org new EventQueue("instruction-based event queue"); 1492SN/A 1502SN/A // 1512SN/A // set up instruction-count-based termination events, if any 1522SN/A // 1535606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1545606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1565606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1576221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1585606Snate@binkert.org } 1595606Snate@binkert.org } 1602SN/A 1611400SN/A if (p->max_insts_all_threads != 0) { 1625606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1635606Snate@binkert.org 1642SN/A // allocate & initialize shared downcounter: each event will 1652SN/A // decrement this when triggered; simulation will terminate 1662SN/A // when counter reaches 0 1672SN/A int *counter = new int; 1686221Snate@binkert.org *counter = numThreads; 1696221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1705606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1716670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1725606Snate@binkert.org } 1732SN/A } 1742SN/A 175124SN/A // allocate per-thread load-based event queues 1766221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1776221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1786221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 179124SN/A 180124SN/A // 181124SN/A // set up instruction-count-based termination events, if any 182124SN/A // 1835606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1845606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1856221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1865606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1876221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1885606Snate@binkert.org } 1895606Snate@binkert.org } 190124SN/A 1911400SN/A if (p->max_loads_all_threads != 0) { 1925606Snate@binkert.org const char *cause = "all threads reached the max load count"; 193124SN/A // allocate & initialize shared downcounter: each event will 194124SN/A // decrement this when triggered; simulation will terminate 195124SN/A // when counter reaches 0 196124SN/A int *counter = new int; 1976221Snate@binkert.org *counter = numThreads; 1986221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1995606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2006221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2015606Snate@binkert.org } 202124SN/A } 203124SN/A 2041191SN/A functionTracingEnabled = false; 2055529Snate@binkert.org if (p->function_trace) { 2068634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2078634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2088634Schris.emmons@arm.com if (!functionTraceStream) 2098634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2108634Schris.emmons@arm.com 2111191SN/A currentFunctionStart = currentFunctionEnd = 0; 2125529Snate@binkert.org functionEntryTick = p->function_trace_start; 2131191SN/A 2145529Snate@binkert.org if (p->function_trace_start == 0) { 2151191SN/A functionTracingEnabled = true; 2161191SN/A } else { 2175606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2185606Snate@binkert.org Event *event = new wrap(this, true); 2195606Snate@binkert.org schedule(event, p->function_trace_start); 2201191SN/A } 2211191SN/A } 2228876Sandreas.hansson@arm.com 2238876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2248876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2258876Sandreas.hansson@arm.com if (!params()->defer_registration && !is_checker) { 2268876Sandreas.hansson@arm.com if (interrupts) { 2278876Sandreas.hansson@arm.com interrupts->setCPU(this); 2288876Sandreas.hansson@arm.com } else { 2298876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2308876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2318876Sandreas.hansson@arm.com } 2328876Sandreas.hansson@arm.com } 2335810Sgblack@eecs.umich.edu 2348779Sgblack@eecs.umich.edu if (FullSystem) { 2358779Sgblack@eecs.umich.edu profileEvent = NULL; 2368779Sgblack@eecs.umich.edu if (params()->profile) 2378779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2388779Sgblack@eecs.umich.edu } 2395529Snate@binkert.org tracer = params()->tracer; 2401917SN/A} 2411191SN/A 2421191SN/Avoid 2431191SN/ABaseCPU::enableFunctionTrace() 2441191SN/A{ 2451191SN/A functionTracingEnabled = true; 2461191SN/A} 2471191SN/A 2481191SN/ABaseCPU::~BaseCPU() 2491191SN/A{ 2501191SN/A} 2511191SN/A 2521129SN/Avoid 2531129SN/ABaseCPU::init() 2541129SN/A{ 2555529Snate@binkert.org if (!params()->defer_registration) 2562680Sktlim@umich.edu registerThreadContexts(); 2571129SN/A} 258180SN/A 2592SN/Avoid 2601917SN/ABaseCPU::startup() 2611917SN/A{ 2628779Sgblack@eecs.umich.edu if (FullSystem) { 2638779Sgblack@eecs.umich.edu if (!params()->defer_registration && profileEvent) 2648779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2658779Sgblack@eecs.umich.edu } 2662356SN/A 2675529Snate@binkert.org if (params()->progress_interval) { 2685606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2696144Sksewell@umich.edu 2708607Sgblack@eecs.umich.edu new CPUProgressEvent(this, num_ticks); 2712356SN/A } 2721917SN/A} 2731917SN/A 2741917SN/A 2751917SN/Avoid 2762SN/ABaseCPU::regStats() 2772SN/A{ 278729SN/A using namespace Stats; 279707SN/A 280707SN/A numCycles 281707SN/A .name(name() + ".numCycles") 282707SN/A .desc("number of cpu cycles simulated") 283707SN/A ; 284707SN/A 2857914SBrad.Beckmann@amd.com numWorkItemsStarted 2867914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2877914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 2887914SBrad.Beckmann@amd.com ; 2897914SBrad.Beckmann@amd.com 2907914SBrad.Beckmann@amd.com numWorkItemsCompleted 2917914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 2927914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 2937914SBrad.Beckmann@amd.com ; 2947914SBrad.Beckmann@amd.com 2952680Sktlim@umich.edu int size = threadContexts.size(); 2962SN/A if (size > 1) { 2972SN/A for (int i = 0; i < size; ++i) { 2982SN/A stringstream namestr; 2992SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 3002680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 3012SN/A } 3022SN/A } else if (size == 1) 3032680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3042SN/A} 3052SN/A 3068850Sandreas.hansson@arm.comPort * 3078850Sandreas.hansson@arm.comBaseCPU::getPort(const string &if_name, int idx) 3088850Sandreas.hansson@arm.com{ 3098850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 3108850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 3118850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 3128850Sandreas.hansson@arm.com // return a CpuPort pointer. 3138850Sandreas.hansson@arm.com if (if_name == "dcache_port") 3148850Sandreas.hansson@arm.com return &getDataPort(); 3158850Sandreas.hansson@arm.com else if (if_name == "icache_port") 3168850Sandreas.hansson@arm.com return &getInstPort(); 3178850Sandreas.hansson@arm.com else 3188850Sandreas.hansson@arm.com panic("CPU %s has no port named %s\n", name(), if_name); 3198850Sandreas.hansson@arm.com} 3208850Sandreas.hansson@arm.com 3213495Sktlim@umich.eduTick 3223495Sktlim@umich.eduBaseCPU::nextCycle() 3233495Sktlim@umich.edu{ 3247823Ssteve.reinhardt@amd.com Tick next_tick = curTick() - phase + clock - 1; 3253495Sktlim@umich.edu next_tick -= (next_tick % clock); 3263661Srdreslin@umich.edu next_tick += phase; 3273495Sktlim@umich.edu return next_tick; 3283495Sktlim@umich.edu} 3293495Sktlim@umich.edu 3303495Sktlim@umich.eduTick 3313495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 3323495Sktlim@umich.edu{ 3333495Sktlim@umich.edu Tick next_tick = begin_tick; 3344599Sacolyte@umich.edu if (next_tick % clock != 0) 3354599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 3363661Srdreslin@umich.edu next_tick += phase; 3373495Sktlim@umich.edu 3387823Ssteve.reinhardt@amd.com assert(next_tick >= curTick()); 3393495Sktlim@umich.edu return next_tick; 3403495Sktlim@umich.edu} 341180SN/A 342180SN/Avoid 3432680Sktlim@umich.eduBaseCPU::registerThreadContexts() 344180SN/A{ 3456221Snate@binkert.org ThreadID size = threadContexts.size(); 3466221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3476221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3482378SN/A 3495718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3505718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3515718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3525718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3535718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3545718Shsul@eecs.umich.edu * I'll just do this for now 3555718Shsul@eecs.umich.edu */ 3566221Snate@binkert.org if (numThreads == 1) 3575718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3585718Shsul@eecs.umich.edu else 3595718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3608779Sgblack@eecs.umich.edu 3618779Sgblack@eecs.umich.edu if (!FullSystem) 3628779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 363180SN/A } 364180SN/A} 365180SN/A 366180SN/A 3674000Ssaidi@eecs.umich.eduint 3684000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3694000Ssaidi@eecs.umich.edu{ 3706221Snate@binkert.org ThreadID size = threadContexts.size(); 3716221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3726221Snate@binkert.org if (tc == threadContexts[tid]) 3736221Snate@binkert.org return tid; 3744000Ssaidi@eecs.umich.edu } 3754000Ssaidi@eecs.umich.edu return 0; 3764000Ssaidi@eecs.umich.edu} 3774000Ssaidi@eecs.umich.edu 378180SN/Avoid 3792798Sktlim@umich.eduBaseCPU::switchOut() 380180SN/A{ 3812359SN/A if (profileEvent && profileEvent->scheduled()) 3825606Snate@binkert.org deschedule(profileEvent); 383180SN/A} 384180SN/A 385180SN/Avoid 3868737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 387180SN/A{ 3888850Sandreas.hansson@arm.com CpuPort &ic = getInstPort(); 3898850Sandreas.hansson@arm.com CpuPort &dc = getDataPort(); 3902680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 391180SN/A 3925712Shsul@eecs.umich.edu _cpuId = oldCPU->cpuId(); 3935712Shsul@eecs.umich.edu 3946221Snate@binkert.org ThreadID size = threadContexts.size(); 3956221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3962680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3972680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 398180SN/A 3992680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 4002651Ssaidi@eecs.umich.edu 4012680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 4022651Ssaidi@eecs.umich.edu 4035714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 4045715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 4055714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 4062359SN/A 4075875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 4085875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 4095875Ssteve.reinhardt@amd.com * point. 4105875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 4115217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 4125875Ssteve.reinhardt@amd.com */ 4137781SAli.Saidi@ARM.com 4147781SAli.Saidi@ARM.com Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; 4157781SAli.Saidi@ARM.com old_itb_port = oldTC->getITBPtr()->getPort(); 4167781SAli.Saidi@ARM.com old_dtb_port = oldTC->getDTBPtr()->getPort(); 4177781SAli.Saidi@ARM.com new_itb_port = newTC->getITBPtr()->getPort(); 4187781SAli.Saidi@ARM.com new_dtb_port = newTC->getDTBPtr()->getPort(); 4197781SAli.Saidi@ARM.com 4207781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 4217781SAli.Saidi@ARM.com if (new_itb_port && !new_itb_port->isConnected()) { 4227781SAli.Saidi@ARM.com assert(old_itb_port); 4237781SAli.Saidi@ARM.com Port *peer = old_itb_port->getPeer();; 4247781SAli.Saidi@ARM.com new_itb_port->setPeer(peer); 4257781SAli.Saidi@ARM.com peer->setPeer(new_itb_port); 4267781SAli.Saidi@ARM.com } 4277781SAli.Saidi@ARM.com if (new_dtb_port && !new_dtb_port->isConnected()) { 4287781SAli.Saidi@ARM.com assert(old_dtb_port); 4297781SAli.Saidi@ARM.com Port *peer = old_dtb_port->getPeer();; 4307781SAli.Saidi@ARM.com new_dtb_port->setPeer(peer); 4317781SAli.Saidi@ARM.com peer->setPeer(new_dtb_port); 4327781SAli.Saidi@ARM.com } 4338733Sgeoffrey.blake@arm.com 4348733Sgeoffrey.blake@arm.com#if USE_CHECKER 4358733Sgeoffrey.blake@arm.com Port *old_checker_itb_port, *old_checker_dtb_port; 4368733Sgeoffrey.blake@arm.com Port *new_checker_itb_port, *new_checker_dtb_port; 4378733Sgeoffrey.blake@arm.com 4388733Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = 4398733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr()); 4408733Sgeoffrey.blake@arm.com CheckerCPU *newChecker = 4418733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr()); 4428733Sgeoffrey.blake@arm.com old_checker_itb_port = oldChecker->getITBPtr()->getPort(); 4438733Sgeoffrey.blake@arm.com old_checker_dtb_port = oldChecker->getDTBPtr()->getPort(); 4448733Sgeoffrey.blake@arm.com new_checker_itb_port = newChecker->getITBPtr()->getPort(); 4458733Sgeoffrey.blake@arm.com new_checker_dtb_port = newChecker->getDTBPtr()->getPort(); 4468733Sgeoffrey.blake@arm.com 4478733Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4488733Sgeoffrey.blake@arm.com if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { 4498733Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4508733Sgeoffrey.blake@arm.com Port *peer = old_checker_itb_port->getPeer();; 4518733Sgeoffrey.blake@arm.com new_checker_itb_port->setPeer(peer); 4528733Sgeoffrey.blake@arm.com peer->setPeer(new_checker_itb_port); 4538733Sgeoffrey.blake@arm.com } 4548733Sgeoffrey.blake@arm.com if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { 4558733Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4568733Sgeoffrey.blake@arm.com Port *peer = old_checker_dtb_port->getPeer();; 4578733Sgeoffrey.blake@arm.com new_checker_dtb_port->setPeer(peer); 4588733Sgeoffrey.blake@arm.com peer->setPeer(new_checker_dtb_port); 4598733Sgeoffrey.blake@arm.com } 4608733Sgeoffrey.blake@arm.com#endif 4618733Sgeoffrey.blake@arm.com 462180SN/A } 463605SN/A 4643520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4655810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4662254SN/A 4678779Sgblack@eecs.umich.edu if (FullSystem) { 4688779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4698779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4702254SN/A 4718779Sgblack@eecs.umich.edu if (profileEvent) 4728779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4738779Sgblack@eecs.umich.edu } 4744192Sktlim@umich.edu 4754192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 4764192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 4774192Sktlim@umich.edu // CPU. 4788850Sandreas.hansson@arm.com if (!ic.isConnected()) { 4798850Sandreas.hansson@arm.com Port *peer = oldCPU->getInstPort().getPeer(); 4808850Sandreas.hansson@arm.com ic.setPeer(peer); 4818850Sandreas.hansson@arm.com peer->setPeer(&ic); 4824192Sktlim@umich.edu } 4834192Sktlim@umich.edu 4848850Sandreas.hansson@arm.com if (!dc.isConnected()) { 4858850Sandreas.hansson@arm.com Port *peer = oldCPU->getDataPort().getPeer(); 4868850Sandreas.hansson@arm.com dc.setPeer(peer); 4878850Sandreas.hansson@arm.com peer->setPeer(&dc); 4884192Sktlim@umich.edu } 489180SN/A} 490180SN/A 491180SN/A 4925536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 4935606Snate@binkert.org : cpu(_cpu), interval(_interval) 4941917SN/A{ } 4951917SN/A 4961917SN/Avoid 4971917SN/ABaseCPU::ProfileEvent::process() 4981917SN/A{ 4996221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 5006221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5012680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 5022680Sktlim@umich.edu tc->profileSample(); 5031917SN/A } 5042254SN/A 5057823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 5061917SN/A} 5071917SN/A 5082SN/Avoid 509921SN/ABaseCPU::serialize(std::ostream &os) 510921SN/A{ 5114000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 5125647Sgblack@eecs.umich.edu interrupts->serialize(os); 513921SN/A} 514921SN/A 515921SN/Avoid 516921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 517921SN/A{ 5184000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5195647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 520921SN/A} 521921SN/A 5221191SN/Avoid 5231191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5241191SN/A{ 5251191SN/A if (!debugSymbolTable) 5261191SN/A return; 5271191SN/A 5281191SN/A // if pc enters different function, print new function symbol and 5291191SN/A // update saved range. Otherwise do nothing. 5301191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5311191SN/A string sym_str; 5321191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5331191SN/A currentFunctionStart, 5341191SN/A currentFunctionEnd); 5351191SN/A 5361191SN/A if (!found) { 5371191SN/A // no symbol found: use addr as label 5381191SN/A sym_str = csprintf("0x%x", pc); 5391191SN/A currentFunctionStart = pc; 5401191SN/A currentFunctionEnd = pc + 1; 5411191SN/A } 5421191SN/A 5431191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 5447823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 5457823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 5461191SN/A } 5471191SN/A} 5488707Sandreas.hansson@arm.com 5498707Sandreas.hansson@arm.combool 5508707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvTiming(PacketPtr pkt) 5518707Sandreas.hansson@arm.com{ 5528707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvTiming callback!"); 5538707Sandreas.hansson@arm.com return true; 5548707Sandreas.hansson@arm.com} 5558707Sandreas.hansson@arm.com 5568707Sandreas.hansson@arm.comvoid 5578707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRetry() 5588707Sandreas.hansson@arm.com{ 5598707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvRetry callback!"); 5608707Sandreas.hansson@arm.com} 5618707Sandreas.hansson@arm.com 5628707Sandreas.hansson@arm.comTick 5638707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvAtomic(PacketPtr pkt) 5648707Sandreas.hansson@arm.com{ 5658707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvAtomic callback!"); 5668707Sandreas.hansson@arm.com return curTick(); 5678707Sandreas.hansson@arm.com} 5688707Sandreas.hansson@arm.com 5698707Sandreas.hansson@arm.comvoid 5708707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvFunctional(PacketPtr pkt) 5718707Sandreas.hansson@arm.com{ 5728707Sandreas.hansson@arm.com // No internal storage to update (in the general case). In the 5738707Sandreas.hansson@arm.com // long term this should never be called, but that assumed a split 5748707Sandreas.hansson@arm.com // into master/slave and request/response. 5758707Sandreas.hansson@arm.com} 5768707Sandreas.hansson@arm.com 5778707Sandreas.hansson@arm.comvoid 5788711Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRangeChange() 5798707Sandreas.hansson@arm.com{ 5808707Sandreas.hansson@arm.com} 581