base.cc revision 8820
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 568733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 571717SN/A#include "cpu/base.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642190SN/A#include "sim/process.hh" 6556SN/A#include "sim/sim_events.hh" 668229Snate@binkert.org#include "sim/sim_exit.hh" 672190SN/A#include "sim/system.hh" 682SN/A 698733Sgeoffrey.blake@arm.com#if USE_CHECKER 708733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 718733Sgeoffrey.blake@arm.com#endif 728733Sgeoffrey.blake@arm.com 732359SN/A// Hack 742359SN/A#include "sim/stat_control.hh" 752359SN/A 762SN/Ausing namespace std; 772SN/A 782SN/Avector<BaseCPU *> BaseCPU::cpuList; 792SN/A 802SN/A// This variable reflects the max number of threads in any CPU. Be 812SN/A// careful to only use it once all the CPUs that you care about have 822SN/A// been initialized 832SN/Aint maxThreadsPerCPU = 1; 842SN/A 855606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 866144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 876144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 883126Sktlim@umich.edu{ 896144Sksewell@umich.edu if (_interval) 907823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 913126Sktlim@umich.edu} 923126Sktlim@umich.edu 932356SN/Avoid 942356SN/ACPUProgressEvent::process() 952356SN/A{ 962367SN/A Counter temp = cpu->totalInstructions(); 972356SN/A#ifndef NDEBUG 986144Sksewell@umich.edu double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 992367SN/A 1006144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1016144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1026144Sksewell@umich.edu ipc); 1032356SN/A ipc = 0.0; 1042367SN/A#else 1056144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1067823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1076144Sksewell@umich.edu temp - lastNumInst); 1082367SN/A#endif 1092356SN/A lastNumInst = temp; 1106144Sksewell@umich.edu 1116144Sksewell@umich.edu if (_repeatEvent) 1127823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1132356SN/A} 1142356SN/A 1152356SN/Aconst char * 1165336Shines@cs.fsu.eduCPUProgressEvent::description() const 1172356SN/A{ 1184873Sstever@eecs.umich.edu return "CPU Progress"; 1192356SN/A} 1202356SN/A 1211400SN/ABaseCPU::BaseCPU(Params *p) 1225712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 1235712Shsul@eecs.umich.edu interrupts(p->interrupts), 1246221Snate@binkert.org numThreads(p->numThreads), system(p->system), 1253661Srdreslin@umich.edu phase(p->phase) 1262SN/A{ 1277823Ssteve.reinhardt@amd.com// currentTick = curTick(); 1281062SN/A 1295712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1305712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1315712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1325712Shsul@eecs.umich.edu } 1335712Shsul@eecs.umich.edu 1342SN/A // add self to global list of CPUs 1352SN/A cpuList.push_back(this); 1362SN/A 1375712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1385712Shsul@eecs.umich.edu 1396221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1406221Snate@binkert.org maxThreadsPerCPU = numThreads; 1412SN/A 1422SN/A // allocate per-thread instruction-based event queues 1436221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1446221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1456221Snate@binkert.org comInstEventQueue[tid] = 1466221Snate@binkert.org new EventQueue("instruction-based event queue"); 1472SN/A 1482SN/A // 1492SN/A // set up instruction-count-based termination events, if any 1502SN/A // 1515606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1525606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1536221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1545606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1556221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1565606Snate@binkert.org } 1575606Snate@binkert.org } 1582SN/A 1591400SN/A if (p->max_insts_all_threads != 0) { 1605606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1615606Snate@binkert.org 1622SN/A // allocate & initialize shared downcounter: each event will 1632SN/A // decrement this when triggered; simulation will terminate 1642SN/A // when counter reaches 0 1652SN/A int *counter = new int; 1666221Snate@binkert.org *counter = numThreads; 1676221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1685606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1696670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1705606Snate@binkert.org } 1712SN/A } 1722SN/A 173124SN/A // allocate per-thread load-based event queues 1746221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1756221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1766221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 177124SN/A 178124SN/A // 179124SN/A // set up instruction-count-based termination events, if any 180124SN/A // 1815606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1825606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1845606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1856221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1865606Snate@binkert.org } 1875606Snate@binkert.org } 188124SN/A 1891400SN/A if (p->max_loads_all_threads != 0) { 1905606Snate@binkert.org const char *cause = "all threads reached the max load count"; 191124SN/A // allocate & initialize shared downcounter: each event will 192124SN/A // decrement this when triggered; simulation will terminate 193124SN/A // when counter reaches 0 194124SN/A int *counter = new int; 1956221Snate@binkert.org *counter = numThreads; 1966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1975606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1986221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 1995606Snate@binkert.org } 200124SN/A } 201124SN/A 2021191SN/A functionTracingEnabled = false; 2035529Snate@binkert.org if (p->function_trace) { 2048634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2058634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2068634Schris.emmons@arm.com if (!functionTraceStream) 2078634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2088634Schris.emmons@arm.com 2091191SN/A currentFunctionStart = currentFunctionEnd = 0; 2105529Snate@binkert.org functionEntryTick = p->function_trace_start; 2111191SN/A 2125529Snate@binkert.org if (p->function_trace_start == 0) { 2131191SN/A functionTracingEnabled = true; 2141191SN/A } else { 2155606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2165606Snate@binkert.org Event *event = new wrap(this, true); 2175606Snate@binkert.org schedule(event, p->function_trace_start); 2181191SN/A } 2191191SN/A } 2208733Sgeoffrey.blake@arm.com // Check if CPU model has interrupts connected. The CheckerCPU 2218733Sgeoffrey.blake@arm.com // cannot take interrupts directly for example. 2228733Sgeoffrey.blake@arm.com if (interrupts) 2238733Sgeoffrey.blake@arm.com interrupts->setCPU(this); 2245810Sgblack@eecs.umich.edu 2258779Sgblack@eecs.umich.edu if (FullSystem) { 2268779Sgblack@eecs.umich.edu profileEvent = NULL; 2278779Sgblack@eecs.umich.edu if (params()->profile) 2288779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2298779Sgblack@eecs.umich.edu } 2305529Snate@binkert.org tracer = params()->tracer; 2311917SN/A} 2321191SN/A 2331191SN/Avoid 2341191SN/ABaseCPU::enableFunctionTrace() 2351191SN/A{ 2361191SN/A functionTracingEnabled = true; 2371191SN/A} 2381191SN/A 2391191SN/ABaseCPU::~BaseCPU() 2401191SN/A{ 2411191SN/A} 2421191SN/A 2431129SN/Avoid 2441129SN/ABaseCPU::init() 2451129SN/A{ 2465529Snate@binkert.org if (!params()->defer_registration) 2472680Sktlim@umich.edu registerThreadContexts(); 2481129SN/A} 249180SN/A 2502SN/Avoid 2511917SN/ABaseCPU::startup() 2521917SN/A{ 2538779Sgblack@eecs.umich.edu if (FullSystem) { 2548779Sgblack@eecs.umich.edu if (!params()->defer_registration && profileEvent) 2558779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2568779Sgblack@eecs.umich.edu } 2572356SN/A 2585529Snate@binkert.org if (params()->progress_interval) { 2595606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2606144Sksewell@umich.edu 2618607Sgblack@eecs.umich.edu new CPUProgressEvent(this, num_ticks); 2622356SN/A } 2631917SN/A} 2641917SN/A 2651917SN/A 2661917SN/Avoid 2672SN/ABaseCPU::regStats() 2682SN/A{ 269729SN/A using namespace Stats; 270707SN/A 271707SN/A numCycles 272707SN/A .name(name() + ".numCycles") 273707SN/A .desc("number of cpu cycles simulated") 274707SN/A ; 275707SN/A 2767914SBrad.Beckmann@amd.com numWorkItemsStarted 2777914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2787914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 2797914SBrad.Beckmann@amd.com ; 2807914SBrad.Beckmann@amd.com 2817914SBrad.Beckmann@amd.com numWorkItemsCompleted 2827914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 2837914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 2847914SBrad.Beckmann@amd.com ; 2857914SBrad.Beckmann@amd.com 2862680Sktlim@umich.edu int size = threadContexts.size(); 2872SN/A if (size > 1) { 2882SN/A for (int i = 0; i < size; ++i) { 2892SN/A stringstream namestr; 2902SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2912680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2922SN/A } 2932SN/A } else if (size == 1) 2942680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2952SN/A} 2962SN/A 2973495Sktlim@umich.eduTick 2983495Sktlim@umich.eduBaseCPU::nextCycle() 2993495Sktlim@umich.edu{ 3007823Ssteve.reinhardt@amd.com Tick next_tick = curTick() - phase + clock - 1; 3013495Sktlim@umich.edu next_tick -= (next_tick % clock); 3023661Srdreslin@umich.edu next_tick += phase; 3033495Sktlim@umich.edu return next_tick; 3043495Sktlim@umich.edu} 3053495Sktlim@umich.edu 3063495Sktlim@umich.eduTick 3073495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 3083495Sktlim@umich.edu{ 3093495Sktlim@umich.edu Tick next_tick = begin_tick; 3104599Sacolyte@umich.edu if (next_tick % clock != 0) 3114599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 3123661Srdreslin@umich.edu next_tick += phase; 3133495Sktlim@umich.edu 3147823Ssteve.reinhardt@amd.com assert(next_tick >= curTick()); 3153495Sktlim@umich.edu return next_tick; 3163495Sktlim@umich.edu} 317180SN/A 318180SN/Avoid 3192680Sktlim@umich.eduBaseCPU::registerThreadContexts() 320180SN/A{ 3216221Snate@binkert.org ThreadID size = threadContexts.size(); 3226221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3236221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3242378SN/A 3255718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3265718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3275718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3285718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3295718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3305718Shsul@eecs.umich.edu * I'll just do this for now 3315718Shsul@eecs.umich.edu */ 3326221Snate@binkert.org if (numThreads == 1) 3335718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3345718Shsul@eecs.umich.edu else 3355718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3368779Sgblack@eecs.umich.edu 3378779Sgblack@eecs.umich.edu if (!FullSystem) 3388779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 339180SN/A } 340180SN/A} 341180SN/A 342180SN/A 3434000Ssaidi@eecs.umich.eduint 3444000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3454000Ssaidi@eecs.umich.edu{ 3466221Snate@binkert.org ThreadID size = threadContexts.size(); 3476221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3486221Snate@binkert.org if (tc == threadContexts[tid]) 3496221Snate@binkert.org return tid; 3504000Ssaidi@eecs.umich.edu } 3514000Ssaidi@eecs.umich.edu return 0; 3524000Ssaidi@eecs.umich.edu} 3534000Ssaidi@eecs.umich.edu 354180SN/Avoid 3552798Sktlim@umich.eduBaseCPU::switchOut() 356180SN/A{ 3572359SN/A if (profileEvent && profileEvent->scheduled()) 3585606Snate@binkert.org deschedule(profileEvent); 359180SN/A} 360180SN/A 361180SN/Avoid 3628737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 363180SN/A{ 3648737Skoansin.tan@gmail.com Port *ic = getPort("icache_port"); 3658737Skoansin.tan@gmail.com Port *dc = getPort("dcache_port"); 3662680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 367180SN/A 3685712Shsul@eecs.umich.edu _cpuId = oldCPU->cpuId(); 3695712Shsul@eecs.umich.edu 3706221Snate@binkert.org ThreadID size = threadContexts.size(); 3716221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3722680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3732680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 374180SN/A 3752680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3762651Ssaidi@eecs.umich.edu 3772680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3782651Ssaidi@eecs.umich.edu 3795714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 3805715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 3815714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 3822359SN/A 3835875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 3845875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 3855875Ssteve.reinhardt@amd.com * point. 3865875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 3875217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 3885875Ssteve.reinhardt@amd.com */ 3897781SAli.Saidi@ARM.com 3907781SAli.Saidi@ARM.com Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; 3917781SAli.Saidi@ARM.com old_itb_port = oldTC->getITBPtr()->getPort(); 3927781SAli.Saidi@ARM.com old_dtb_port = oldTC->getDTBPtr()->getPort(); 3937781SAli.Saidi@ARM.com new_itb_port = newTC->getITBPtr()->getPort(); 3947781SAli.Saidi@ARM.com new_dtb_port = newTC->getDTBPtr()->getPort(); 3957781SAli.Saidi@ARM.com 3967781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 3977781SAli.Saidi@ARM.com if (new_itb_port && !new_itb_port->isConnected()) { 3987781SAli.Saidi@ARM.com assert(old_itb_port); 3997781SAli.Saidi@ARM.com Port *peer = old_itb_port->getPeer();; 4007781SAli.Saidi@ARM.com new_itb_port->setPeer(peer); 4017781SAli.Saidi@ARM.com peer->setPeer(new_itb_port); 4027781SAli.Saidi@ARM.com } 4037781SAli.Saidi@ARM.com if (new_dtb_port && !new_dtb_port->isConnected()) { 4047781SAli.Saidi@ARM.com assert(old_dtb_port); 4057781SAli.Saidi@ARM.com Port *peer = old_dtb_port->getPeer();; 4067781SAli.Saidi@ARM.com new_dtb_port->setPeer(peer); 4077781SAli.Saidi@ARM.com peer->setPeer(new_dtb_port); 4087781SAli.Saidi@ARM.com } 4098733Sgeoffrey.blake@arm.com 4108733Sgeoffrey.blake@arm.com#if USE_CHECKER 4118733Sgeoffrey.blake@arm.com Port *old_checker_itb_port, *old_checker_dtb_port; 4128733Sgeoffrey.blake@arm.com Port *new_checker_itb_port, *new_checker_dtb_port; 4138733Sgeoffrey.blake@arm.com 4148733Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = 4158733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr()); 4168733Sgeoffrey.blake@arm.com CheckerCPU *newChecker = 4178733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr()); 4188733Sgeoffrey.blake@arm.com old_checker_itb_port = oldChecker->getITBPtr()->getPort(); 4198733Sgeoffrey.blake@arm.com old_checker_dtb_port = oldChecker->getDTBPtr()->getPort(); 4208733Sgeoffrey.blake@arm.com new_checker_itb_port = newChecker->getITBPtr()->getPort(); 4218733Sgeoffrey.blake@arm.com new_checker_dtb_port = newChecker->getDTBPtr()->getPort(); 4228733Sgeoffrey.blake@arm.com 4238733Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4248733Sgeoffrey.blake@arm.com if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { 4258733Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4268733Sgeoffrey.blake@arm.com Port *peer = old_checker_itb_port->getPeer();; 4278733Sgeoffrey.blake@arm.com new_checker_itb_port->setPeer(peer); 4288733Sgeoffrey.blake@arm.com peer->setPeer(new_checker_itb_port); 4298733Sgeoffrey.blake@arm.com } 4308733Sgeoffrey.blake@arm.com if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { 4318733Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4328733Sgeoffrey.blake@arm.com Port *peer = old_checker_dtb_port->getPeer();; 4338733Sgeoffrey.blake@arm.com new_checker_dtb_port->setPeer(peer); 4348733Sgeoffrey.blake@arm.com peer->setPeer(new_checker_dtb_port); 4358733Sgeoffrey.blake@arm.com } 4368733Sgeoffrey.blake@arm.com#endif 4378733Sgeoffrey.blake@arm.com 438180SN/A } 439605SN/A 4403520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4415810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4422254SN/A 4438779Sgblack@eecs.umich.edu if (FullSystem) { 4448779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4458779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4462254SN/A 4478779Sgblack@eecs.umich.edu if (profileEvent) 4488779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4498779Sgblack@eecs.umich.edu } 4504192Sktlim@umich.edu 4514192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 4524192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 4534192Sktlim@umich.edu // CPU. 4545476Snate@binkert.org if (!ic->isConnected()) { 4555476Snate@binkert.org Port *peer = oldCPU->getPort("icache_port")->getPeer(); 4564192Sktlim@umich.edu ic->setPeer(peer); 4575476Snate@binkert.org peer->setPeer(ic); 4584192Sktlim@umich.edu } 4594192Sktlim@umich.edu 4605476Snate@binkert.org if (!dc->isConnected()) { 4615476Snate@binkert.org Port *peer = oldCPU->getPort("dcache_port")->getPeer(); 4624192Sktlim@umich.edu dc->setPeer(peer); 4635476Snate@binkert.org peer->setPeer(dc); 4644192Sktlim@umich.edu } 465180SN/A} 466180SN/A 467180SN/A 4685536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 4695606Snate@binkert.org : cpu(_cpu), interval(_interval) 4701917SN/A{ } 4711917SN/A 4721917SN/Avoid 4731917SN/ABaseCPU::ProfileEvent::process() 4741917SN/A{ 4756221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 4766221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4772680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 4782680Sktlim@umich.edu tc->profileSample(); 4791917SN/A } 4802254SN/A 4817823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 4821917SN/A} 4831917SN/A 4842SN/Avoid 485921SN/ABaseCPU::serialize(std::ostream &os) 486921SN/A{ 4874000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 4885647Sgblack@eecs.umich.edu interrupts->serialize(os); 489921SN/A} 490921SN/A 491921SN/Avoid 492921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 493921SN/A{ 4944000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 4955647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 496921SN/A} 497921SN/A 4981191SN/Avoid 4991191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5001191SN/A{ 5011191SN/A if (!debugSymbolTable) 5021191SN/A return; 5031191SN/A 5041191SN/A // if pc enters different function, print new function symbol and 5051191SN/A // update saved range. Otherwise do nothing. 5061191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5071191SN/A string sym_str; 5081191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5091191SN/A currentFunctionStart, 5101191SN/A currentFunctionEnd); 5111191SN/A 5121191SN/A if (!found) { 5131191SN/A // no symbol found: use addr as label 5141191SN/A sym_str = csprintf("0x%x", pc); 5151191SN/A currentFunctionStart = pc; 5161191SN/A currentFunctionEnd = pc + 1; 5171191SN/A } 5181191SN/A 5191191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 5207823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 5217823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 5221191SN/A } 5231191SN/A} 5248707Sandreas.hansson@arm.com 5258707Sandreas.hansson@arm.combool 5268707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvTiming(PacketPtr pkt) 5278707Sandreas.hansson@arm.com{ 5288707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvTiming callback!"); 5298707Sandreas.hansson@arm.com return true; 5308707Sandreas.hansson@arm.com} 5318707Sandreas.hansson@arm.com 5328707Sandreas.hansson@arm.comvoid 5338707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRetry() 5348707Sandreas.hansson@arm.com{ 5358707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvRetry callback!"); 5368707Sandreas.hansson@arm.com} 5378707Sandreas.hansson@arm.com 5388707Sandreas.hansson@arm.comTick 5398707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvAtomic(PacketPtr pkt) 5408707Sandreas.hansson@arm.com{ 5418707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvAtomic callback!"); 5428707Sandreas.hansson@arm.com return curTick(); 5438707Sandreas.hansson@arm.com} 5448707Sandreas.hansson@arm.com 5458707Sandreas.hansson@arm.comvoid 5468707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvFunctional(PacketPtr pkt) 5478707Sandreas.hansson@arm.com{ 5488707Sandreas.hansson@arm.com // No internal storage to update (in the general case). In the 5498707Sandreas.hansson@arm.com // long term this should never be called, but that assumed a split 5508707Sandreas.hansson@arm.com // into master/slave and request/response. 5518707Sandreas.hansson@arm.com} 5528707Sandreas.hansson@arm.com 5538707Sandreas.hansson@arm.comvoid 5548711Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRangeChange() 5558707Sandreas.hansson@arm.com{ 5568707Sandreas.hansson@arm.com} 557