base.cc revision 5807
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 405529Snate@binkert.org#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 422651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 441977SN/A#include "cpu/profile.hh" 455529Snate@binkert.org#include "params/BaseCPU.hh" 463144Shsul@eecs.umich.edu#include "sim/sim_exit.hh" 472190SN/A#include "sim/process.hh" 4856SN/A#include "sim/sim_events.hh" 492190SN/A#include "sim/system.hh" 502SN/A 512359SN/A// Hack 522359SN/A#include "sim/stat_control.hh" 532359SN/A 542SN/Ausing namespace std; 552SN/A 562SN/Avector<BaseCPU *> BaseCPU::cpuList; 572SN/A 582SN/A// This variable reflects the max number of threads in any CPU. Be 592SN/A// careful to only use it once all the CPUs that you care about have 602SN/A// been initialized 612SN/Aint maxThreadsPerCPU = 1; 622SN/A 635606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 645606Snate@binkert.org : Event(Event::Progress_Event_Pri), interval(ival), lastNumInst(0), 655606Snate@binkert.org cpu(_cpu) 663126Sktlim@umich.edu{ 673126Sktlim@umich.edu if (interval) 685606Snate@binkert.org cpu->schedule(this, curTick + interval); 693126Sktlim@umich.edu} 703126Sktlim@umich.edu 712356SN/Avoid 722356SN/ACPUProgressEvent::process() 732356SN/A{ 742367SN/A Counter temp = cpu->totalInstructions(); 752356SN/A#ifndef NDEBUG 765100Ssaidi@eecs.umich.edu double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1)); 772367SN/A 782356SN/A DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 792356SN/A cpu->name(), temp - lastNumInst, ipc); 802356SN/A ipc = 0.0; 812367SN/A#else 822367SN/A cprintf("%lli: %s progress event, instructions committed: %lli\n", 832367SN/A curTick, cpu->name(), temp - lastNumInst); 842367SN/A#endif 852356SN/A lastNumInst = temp; 865606Snate@binkert.org cpu->schedule(this, curTick + interval); 872356SN/A} 882356SN/A 892356SN/Aconst char * 905336Shines@cs.fsu.eduCPUProgressEvent::description() const 912356SN/A{ 924873Sstever@eecs.umich.edu return "CPU Progress"; 932356SN/A} 942356SN/A 951858SN/A#if FULL_SYSTEM 961400SN/ABaseCPU::BaseCPU(Params *p) 975712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 985712Shsul@eecs.umich.edu interrupts(p->interrupts), 995529Snate@binkert.org number_of_threads(p->numThreads), system(p->system), 1003661Srdreslin@umich.edu phase(p->phase) 1012SN/A#else 1021400SN/ABaseCPU::BaseCPU(Params *p) 1035712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), _cpuId(p->cpu_id), 1045529Snate@binkert.org number_of_threads(p->numThreads), system(p->system), 1053661Srdreslin@umich.edu phase(p->phase) 1062SN/A#endif 1072SN/A{ 1082359SN/A// currentTick = curTick; 1091062SN/A 1105712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1115712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1125712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1135712Shsul@eecs.umich.edu } 1145712Shsul@eecs.umich.edu 1152SN/A // add self to global list of CPUs 1162SN/A cpuList.push_back(this); 1172SN/A 1185712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1195712Shsul@eecs.umich.edu 1202SN/A if (number_of_threads > maxThreadsPerCPU) 1212SN/A maxThreadsPerCPU = number_of_threads; 1222SN/A 1232SN/A // allocate per-thread instruction-based event queues 1241354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 1252SN/A for (int i = 0; i < number_of_threads; ++i) 126503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 1272SN/A 1282SN/A // 1292SN/A // set up instruction-count-based termination events, if any 1302SN/A // 1315606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1325606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1335606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1345606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1355606Snate@binkert.org comInstEventQueue[i]->schedule(event, p->max_insts_any_thread); 1365606Snate@binkert.org } 1375606Snate@binkert.org } 1382SN/A 1391400SN/A if (p->max_insts_all_threads != 0) { 1405606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1415606Snate@binkert.org 1422SN/A // allocate & initialize shared downcounter: each event will 1432SN/A // decrement this when triggered; simulation will terminate 1442SN/A // when counter reaches 0 1452SN/A int *counter = new int; 1462SN/A *counter = number_of_threads; 1475606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1485606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1495606Snate@binkert.org comInstEventQueue[i]->schedule(event, p->max_insts_any_thread); 1505606Snate@binkert.org } 1512SN/A } 1522SN/A 153124SN/A // allocate per-thread load-based event queues 1541354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 155124SN/A for (int i = 0; i < number_of_threads; ++i) 156124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 157124SN/A 158124SN/A // 159124SN/A // set up instruction-count-based termination events, if any 160124SN/A // 1615606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1625606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1635606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1645606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1655606Snate@binkert.org comLoadEventQueue[i]->schedule(event, p->max_loads_any_thread); 1665606Snate@binkert.org } 1675606Snate@binkert.org } 168124SN/A 1691400SN/A if (p->max_loads_all_threads != 0) { 1705606Snate@binkert.org const char *cause = "all threads reached the max load count"; 171124SN/A // allocate & initialize shared downcounter: each event will 172124SN/A // decrement this when triggered; simulation will terminate 173124SN/A // when counter reaches 0 174124SN/A int *counter = new int; 175124SN/A *counter = number_of_threads; 1765606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1775606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1785606Snate@binkert.org comLoadEventQueue[i]->schedule(event, p->max_loads_all_threads); 1795606Snate@binkert.org } 180124SN/A } 181124SN/A 1821191SN/A functionTracingEnabled = false; 1835529Snate@binkert.org if (p->function_trace) { 1841388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1851191SN/A currentFunctionStart = currentFunctionEnd = 0; 1865529Snate@binkert.org functionEntryTick = p->function_trace_start; 1871191SN/A 1885529Snate@binkert.org if (p->function_trace_start == 0) { 1891191SN/A functionTracingEnabled = true; 1901191SN/A } else { 1915606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 1925606Snate@binkert.org Event *event = new wrap(this, true); 1935606Snate@binkert.org schedule(event, p->function_trace_start); 1941191SN/A } 1951191SN/A } 1961917SN/A#if FULL_SYSTEM 1971917SN/A profileEvent = NULL; 1985529Snate@binkert.org if (params()->profile) 1995529Snate@binkert.org profileEvent = new ProfileEvent(this, params()->profile); 2001917SN/A#endif 2015529Snate@binkert.org tracer = params()->tracer; 2021917SN/A} 2031191SN/A 2041191SN/Avoid 2051191SN/ABaseCPU::enableFunctionTrace() 2061191SN/A{ 2071191SN/A functionTracingEnabled = true; 2081191SN/A} 2091191SN/A 2101191SN/ABaseCPU::~BaseCPU() 2111191SN/A{ 2121191SN/A} 2131191SN/A 2141129SN/Avoid 2151129SN/ABaseCPU::init() 2161129SN/A{ 2175529Snate@binkert.org if (!params()->defer_registration) 2182680Sktlim@umich.edu registerThreadContexts(); 2191129SN/A} 220180SN/A 2212SN/Avoid 2221917SN/ABaseCPU::startup() 2231917SN/A{ 2241917SN/A#if FULL_SYSTEM 2255529Snate@binkert.org if (!params()->defer_registration && profileEvent) 2265606Snate@binkert.org schedule(profileEvent, curTick); 2271917SN/A#endif 2282356SN/A 2295529Snate@binkert.org if (params()->progress_interval) { 2305606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2315606Snate@binkert.org Event *event = new CPUProgressEvent(this, num_ticks); 2325606Snate@binkert.org schedule(event, curTick + num_ticks); 2332356SN/A } 2341917SN/A} 2351917SN/A 2361917SN/A 2371917SN/Avoid 2382SN/ABaseCPU::regStats() 2392SN/A{ 240729SN/A using namespace Stats; 241707SN/A 242707SN/A numCycles 243707SN/A .name(name() + ".numCycles") 244707SN/A .desc("number of cpu cycles simulated") 245707SN/A ; 246707SN/A 2472680Sktlim@umich.edu int size = threadContexts.size(); 2482SN/A if (size > 1) { 2492SN/A for (int i = 0; i < size; ++i) { 2502SN/A stringstream namestr; 2512SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2522680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2532SN/A } 2542SN/A } else if (size == 1) 2552680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2562190SN/A 2572190SN/A#if FULL_SYSTEM 2582190SN/A#endif 2592SN/A} 2602SN/A 2613495Sktlim@umich.eduTick 2623495Sktlim@umich.eduBaseCPU::nextCycle() 2633495Sktlim@umich.edu{ 2643661Srdreslin@umich.edu Tick next_tick = curTick - phase + clock - 1; 2653495Sktlim@umich.edu next_tick -= (next_tick % clock); 2663661Srdreslin@umich.edu next_tick += phase; 2673495Sktlim@umich.edu return next_tick; 2683495Sktlim@umich.edu} 2693495Sktlim@umich.edu 2703495Sktlim@umich.eduTick 2713495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 2723495Sktlim@umich.edu{ 2733495Sktlim@umich.edu Tick next_tick = begin_tick; 2744599Sacolyte@umich.edu if (next_tick % clock != 0) 2754599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 2763661Srdreslin@umich.edu next_tick += phase; 2773495Sktlim@umich.edu 2783495Sktlim@umich.edu assert(next_tick >= curTick); 2793495Sktlim@umich.edu return next_tick; 2803495Sktlim@umich.edu} 281180SN/A 282180SN/Avoid 2832680Sktlim@umich.eduBaseCPU::registerThreadContexts() 284180SN/A{ 2852680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2862680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2872378SN/A 2885718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 2895718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 2905718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 2915718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 2925718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 2935718Shsul@eecs.umich.edu * I'll just do this for now 2945718Shsul@eecs.umich.edu */ 2955718Shsul@eecs.umich.edu if (number_of_threads == 1) 2965718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 2975718Shsul@eecs.umich.edu else 2985718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 2995713Shsul@eecs.umich.edu#if !FULL_SYSTEM 3005714Shsul@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 301180SN/A#endif 302180SN/A } 303180SN/A} 304180SN/A 305180SN/A 3064000Ssaidi@eecs.umich.eduint 3074000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3084000Ssaidi@eecs.umich.edu{ 3094000Ssaidi@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3104000Ssaidi@eecs.umich.edu if (tc == threadContexts[i]) 3114000Ssaidi@eecs.umich.edu return i; 3124000Ssaidi@eecs.umich.edu } 3134000Ssaidi@eecs.umich.edu return 0; 3144000Ssaidi@eecs.umich.edu} 3154000Ssaidi@eecs.umich.edu 316180SN/Avoid 3172798Sktlim@umich.eduBaseCPU::switchOut() 318180SN/A{ 3192359SN/A// panic("This CPU doesn't support sampling!"); 3202359SN/A#if FULL_SYSTEM 3212359SN/A if (profileEvent && profileEvent->scheduled()) 3225606Snate@binkert.org deschedule(profileEvent); 3232359SN/A#endif 324180SN/A} 325180SN/A 326180SN/Avoid 3274192Sktlim@umich.eduBaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) 328180SN/A{ 3292680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 330180SN/A 3315712Shsul@eecs.umich.edu _cpuId = oldCPU->cpuId(); 3325712Shsul@eecs.umich.edu 3332680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3342680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3352680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 336180SN/A 3372680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3382651Ssaidi@eecs.umich.edu 3392680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3402651Ssaidi@eecs.umich.edu 3415714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 3425715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 3435714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 3442359SN/A 3455217Ssaidi@eecs.umich.edu if (DTRACE(Context)) 3465217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 347180SN/A } 348605SN/A 3491858SN/A#if FULL_SYSTEM 3503520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 3512254SN/A 3522680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 3532680Sktlim@umich.edu threadContexts[i]->profileClear(); 3542254SN/A 3554947Snate@binkert.org if (profileEvent) 3565606Snate@binkert.org schedule(profileEvent, curTick); 357612SN/A#endif 3584192Sktlim@umich.edu 3594192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 3604192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 3614192Sktlim@umich.edu // CPU. 3625476Snate@binkert.org if (!ic->isConnected()) { 3635476Snate@binkert.org Port *peer = oldCPU->getPort("icache_port")->getPeer(); 3644192Sktlim@umich.edu ic->setPeer(peer); 3655476Snate@binkert.org peer->setPeer(ic); 3664192Sktlim@umich.edu } 3674192Sktlim@umich.edu 3685476Snate@binkert.org if (!dc->isConnected()) { 3695476Snate@binkert.org Port *peer = oldCPU->getPort("dcache_port")->getPeer(); 3704192Sktlim@umich.edu dc->setPeer(peer); 3715476Snate@binkert.org peer->setPeer(dc); 3724192Sktlim@umich.edu } 373180SN/A} 374180SN/A 375180SN/A 3761858SN/A#if FULL_SYSTEM 3775536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 3785606Snate@binkert.org : cpu(_cpu), interval(_interval) 3791917SN/A{ } 3801917SN/A 3811917SN/Avoid 3821917SN/ABaseCPU::ProfileEvent::process() 3831917SN/A{ 3842680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 3852680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 3862680Sktlim@umich.edu tc->profileSample(); 3871917SN/A } 3882254SN/A 3895606Snate@binkert.org cpu->schedule(this, curTick + interval); 3901917SN/A} 3911917SN/A 3922SN/Avoid 393921SN/ABaseCPU::serialize(std::ostream &os) 394921SN/A{ 3954000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 3965647Sgblack@eecs.umich.edu interrupts->serialize(os); 397921SN/A} 398921SN/A 399921SN/Avoid 400921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 401921SN/A{ 4024000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 4035647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 404921SN/A} 405921SN/A 4062SN/A#endif // FULL_SYSTEM 4072SN/A 4081191SN/Avoid 4091191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 4101191SN/A{ 4111191SN/A if (!debugSymbolTable) 4121191SN/A return; 4131191SN/A 4141191SN/A // if pc enters different function, print new function symbol and 4151191SN/A // update saved range. Otherwise do nothing. 4161191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 4171191SN/A string sym_str; 4181191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 4191191SN/A currentFunctionStart, 4201191SN/A currentFunctionEnd); 4211191SN/A 4221191SN/A if (!found) { 4231191SN/A // no symbol found: use addr as label 4241191SN/A sym_str = csprintf("0x%x", pc); 4251191SN/A currentFunctionStart = pc; 4261191SN/A currentFunctionEnd = pc + 1; 4271191SN/A } 4281191SN/A 4291191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 4301191SN/A curTick - functionEntryTick, curTick, sym_str); 4311191SN/A functionEntryTick = curTick; 4321191SN/A } 4331191SN/A} 434