base.cc revision 5704
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 405529Snate@binkert.org#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 422651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 441977SN/A#include "cpu/profile.hh" 455529Snate@binkert.org#include "params/BaseCPU.hh" 463144Shsul@eecs.umich.edu#include "sim/sim_exit.hh" 472190SN/A#include "sim/process.hh" 4856SN/A#include "sim/sim_events.hh" 492190SN/A#include "sim/system.hh" 502SN/A 512359SN/A// Hack 522359SN/A#include "sim/stat_control.hh" 532359SN/A 542SN/Ausing namespace std; 552SN/A 562SN/Avector<BaseCPU *> BaseCPU::cpuList; 572SN/A 582SN/A// This variable reflects the max number of threads in any CPU. Be 592SN/A// careful to only use it once all the CPUs that you care about have 602SN/A// been initialized 612SN/Aint maxThreadsPerCPU = 1; 622SN/A 635606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 645606Snate@binkert.org : Event(Event::Progress_Event_Pri), interval(ival), lastNumInst(0), 655606Snate@binkert.org cpu(_cpu) 663126Sktlim@umich.edu{ 673126Sktlim@umich.edu if (interval) 685606Snate@binkert.org cpu->schedule(this, curTick + interval); 693126Sktlim@umich.edu} 703126Sktlim@umich.edu 712356SN/Avoid 722356SN/ACPUProgressEvent::process() 732356SN/A{ 742367SN/A Counter temp = cpu->totalInstructions(); 752356SN/A#ifndef NDEBUG 765100Ssaidi@eecs.umich.edu double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1)); 772367SN/A 782356SN/A DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 792356SN/A cpu->name(), temp - lastNumInst, ipc); 802356SN/A ipc = 0.0; 812367SN/A#else 822367SN/A cprintf("%lli: %s progress event, instructions committed: %lli\n", 832367SN/A curTick, cpu->name(), temp - lastNumInst); 842367SN/A#endif 852356SN/A lastNumInst = temp; 865606Snate@binkert.org cpu->schedule(this, curTick + interval); 872356SN/A} 882356SN/A 892356SN/Aconst char * 905336Shines@cs.fsu.eduCPUProgressEvent::description() const 912356SN/A{ 924873Sstever@eecs.umich.edu return "CPU Progress"; 932356SN/A} 942356SN/A 951858SN/A#if FULL_SYSTEM 961400SN/ABaseCPU::BaseCPU(Params *p) 975647Sgblack@eecs.umich.edu : MemObject(p), clock(p->clock), instCnt(0), interrupts(p->interrupts), 985529Snate@binkert.org number_of_threads(p->numThreads), system(p->system), 993661Srdreslin@umich.edu phase(p->phase) 1002SN/A#else 1011400SN/ABaseCPU::BaseCPU(Params *p) 1025529Snate@binkert.org : MemObject(p), clock(p->clock), 1035529Snate@binkert.org number_of_threads(p->numThreads), system(p->system), 1043661Srdreslin@umich.edu phase(p->phase) 1052SN/A#endif 1062SN/A{ 1072359SN/A// currentTick = curTick; 1081062SN/A 1092SN/A // add self to global list of CPUs 1102SN/A cpuList.push_back(this); 1112SN/A 1122SN/A if (number_of_threads > maxThreadsPerCPU) 1132SN/A maxThreadsPerCPU = number_of_threads; 1142SN/A 1152SN/A // allocate per-thread instruction-based event queues 1161354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 1172SN/A for (int i = 0; i < number_of_threads; ++i) 118503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 1192SN/A 1202SN/A // 1212SN/A // set up instruction-count-based termination events, if any 1222SN/A // 1235606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1245606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1255606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1265606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1275606Snate@binkert.org comInstEventQueue[i]->schedule(event, p->max_insts_any_thread); 1285606Snate@binkert.org } 1295606Snate@binkert.org } 1302SN/A 1311400SN/A if (p->max_insts_all_threads != 0) { 1325606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1335606Snate@binkert.org 1342SN/A // allocate & initialize shared downcounter: each event will 1352SN/A // decrement this when triggered; simulation will terminate 1362SN/A // when counter reaches 0 1372SN/A int *counter = new int; 1382SN/A *counter = number_of_threads; 1395606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1405606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1415606Snate@binkert.org comInstEventQueue[i]->schedule(event, p->max_insts_any_thread); 1425606Snate@binkert.org } 1432SN/A } 1442SN/A 145124SN/A // allocate per-thread load-based event queues 1461354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 147124SN/A for (int i = 0; i < number_of_threads; ++i) 148124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 149124SN/A 150124SN/A // 151124SN/A // set up instruction-count-based termination events, if any 152124SN/A // 1535606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1545606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1555606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1565606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1575606Snate@binkert.org comLoadEventQueue[i]->schedule(event, p->max_loads_any_thread); 1585606Snate@binkert.org } 1595606Snate@binkert.org } 160124SN/A 1611400SN/A if (p->max_loads_all_threads != 0) { 1625606Snate@binkert.org const char *cause = "all threads reached the max load count"; 163124SN/A // allocate & initialize shared downcounter: each event will 164124SN/A // decrement this when triggered; simulation will terminate 165124SN/A // when counter reaches 0 166124SN/A int *counter = new int; 167124SN/A *counter = number_of_threads; 1685606Snate@binkert.org for (int i = 0; i < number_of_threads; ++i) { 1695606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1705606Snate@binkert.org comLoadEventQueue[i]->schedule(event, p->max_loads_all_threads); 1715606Snate@binkert.org } 172124SN/A } 173124SN/A 1741191SN/A functionTracingEnabled = false; 1755529Snate@binkert.org if (p->function_trace) { 1761388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1771191SN/A currentFunctionStart = currentFunctionEnd = 0; 1785529Snate@binkert.org functionEntryTick = p->function_trace_start; 1791191SN/A 1805529Snate@binkert.org if (p->function_trace_start == 0) { 1811191SN/A functionTracingEnabled = true; 1821191SN/A } else { 1835606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 1845606Snate@binkert.org Event *event = new wrap(this, true); 1855606Snate@binkert.org schedule(event, p->function_trace_start); 1861191SN/A } 1871191SN/A } 1881917SN/A#if FULL_SYSTEM 1891917SN/A profileEvent = NULL; 1905529Snate@binkert.org if (params()->profile) 1915529Snate@binkert.org profileEvent = new ProfileEvent(this, params()->profile); 1921917SN/A#endif 1935529Snate@binkert.org tracer = params()->tracer; 1941917SN/A} 1951191SN/A 1961191SN/Avoid 1971191SN/ABaseCPU::enableFunctionTrace() 1981191SN/A{ 1991191SN/A functionTracingEnabled = true; 2001191SN/A} 2011191SN/A 2021191SN/ABaseCPU::~BaseCPU() 2031191SN/A{ 2041191SN/A} 2051191SN/A 2061129SN/Avoid 2071129SN/ABaseCPU::init() 2081129SN/A{ 2095529Snate@binkert.org if (!params()->defer_registration) 2102680Sktlim@umich.edu registerThreadContexts(); 2111129SN/A} 212180SN/A 2132SN/Avoid 2141917SN/ABaseCPU::startup() 2151917SN/A{ 2161917SN/A#if FULL_SYSTEM 2175529Snate@binkert.org if (!params()->defer_registration && profileEvent) 2185606Snate@binkert.org schedule(profileEvent, curTick); 2191917SN/A#endif 2202356SN/A 2215529Snate@binkert.org if (params()->progress_interval) { 2225606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2235606Snate@binkert.org Event *event = new CPUProgressEvent(this, num_ticks); 2245606Snate@binkert.org schedule(event, curTick + num_ticks); 2252356SN/A } 2261917SN/A} 2271917SN/A 2281917SN/A 2291917SN/Avoid 2302SN/ABaseCPU::regStats() 2312SN/A{ 232729SN/A using namespace Stats; 233707SN/A 234707SN/A numCycles 235707SN/A .name(name() + ".numCycles") 236707SN/A .desc("number of cpu cycles simulated") 237707SN/A ; 238707SN/A 2392680Sktlim@umich.edu int size = threadContexts.size(); 2402SN/A if (size > 1) { 2412SN/A for (int i = 0; i < size; ++i) { 2422SN/A stringstream namestr; 2432SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2442680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2452SN/A } 2462SN/A } else if (size == 1) 2472680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2482190SN/A 2492190SN/A#if FULL_SYSTEM 2502190SN/A#endif 2512SN/A} 2522SN/A 2533495Sktlim@umich.eduTick 2543495Sktlim@umich.eduBaseCPU::nextCycle() 2553495Sktlim@umich.edu{ 2563661Srdreslin@umich.edu Tick next_tick = curTick - phase + clock - 1; 2573495Sktlim@umich.edu next_tick -= (next_tick % clock); 2583661Srdreslin@umich.edu next_tick += phase; 2593495Sktlim@umich.edu return next_tick; 2603495Sktlim@umich.edu} 2613495Sktlim@umich.edu 2623495Sktlim@umich.eduTick 2633495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 2643495Sktlim@umich.edu{ 2653495Sktlim@umich.edu Tick next_tick = begin_tick; 2664599Sacolyte@umich.edu if (next_tick % clock != 0) 2674599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 2683661Srdreslin@umich.edu next_tick += phase; 2693495Sktlim@umich.edu 2703495Sktlim@umich.edu assert(next_tick >= curTick); 2713495Sktlim@umich.edu return next_tick; 2723495Sktlim@umich.edu} 273180SN/A 274180SN/Avoid 2752680Sktlim@umich.eduBaseCPU::registerThreadContexts() 276180SN/A{ 2772680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2782680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2792378SN/A 2801858SN/A#if FULL_SYSTEM 2815529Snate@binkert.org int id = params()->cpu_id; 2821806SN/A if (id != -1) 2831806SN/A id += i; 284180SN/A 2852680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 286180SN/A#else 2872680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 288180SN/A#endif 289180SN/A } 290180SN/A} 291180SN/A 292180SN/A 2934000Ssaidi@eecs.umich.eduint 2944000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 2954000Ssaidi@eecs.umich.edu{ 2964000Ssaidi@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2974000Ssaidi@eecs.umich.edu if (tc == threadContexts[i]) 2984000Ssaidi@eecs.umich.edu return i; 2994000Ssaidi@eecs.umich.edu } 3004000Ssaidi@eecs.umich.edu return 0; 3014000Ssaidi@eecs.umich.edu} 3024000Ssaidi@eecs.umich.edu 303180SN/Avoid 3042798Sktlim@umich.eduBaseCPU::switchOut() 305180SN/A{ 3062359SN/A// panic("This CPU doesn't support sampling!"); 3072359SN/A#if FULL_SYSTEM 3082359SN/A if (profileEvent && profileEvent->scheduled()) 3095606Snate@binkert.org deschedule(profileEvent); 3102359SN/A#endif 311180SN/A} 312180SN/A 313180SN/Avoid 3144192Sktlim@umich.eduBaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) 315180SN/A{ 3162680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 317180SN/A 3182680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3192680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3202680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 321180SN/A 3222680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3232651Ssaidi@eecs.umich.edu 3242680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3252651Ssaidi@eecs.umich.edu 3262680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 3271858SN/A#if FULL_SYSTEM 3282680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 329180SN/A#else 3302680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 3312680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 332180SN/A#endif 3332359SN/A 3345217Ssaidi@eecs.umich.edu if (DTRACE(Context)) 3355217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 336180SN/A } 337605SN/A 3381858SN/A#if FULL_SYSTEM 3393520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 3402254SN/A 3412680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 3422680Sktlim@umich.edu threadContexts[i]->profileClear(); 3432254SN/A 3444947Snate@binkert.org if (profileEvent) 3455606Snate@binkert.org schedule(profileEvent, curTick); 346612SN/A#endif 3474192Sktlim@umich.edu 3484192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 3494192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 3504192Sktlim@umich.edu // CPU. 3515476Snate@binkert.org if (!ic->isConnected()) { 3525476Snate@binkert.org Port *peer = oldCPU->getPort("icache_port")->getPeer(); 3534192Sktlim@umich.edu ic->setPeer(peer); 3545476Snate@binkert.org peer->setPeer(ic); 3554192Sktlim@umich.edu } 3564192Sktlim@umich.edu 3575476Snate@binkert.org if (!dc->isConnected()) { 3585476Snate@binkert.org Port *peer = oldCPU->getPort("dcache_port")->getPeer(); 3594192Sktlim@umich.edu dc->setPeer(peer); 3605476Snate@binkert.org peer->setPeer(dc); 3614192Sktlim@umich.edu } 362180SN/A} 363180SN/A 364180SN/A 3651858SN/A#if FULL_SYSTEM 3665536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 3675606Snate@binkert.org : cpu(_cpu), interval(_interval) 3681917SN/A{ } 3691917SN/A 3701917SN/Avoid 3711917SN/ABaseCPU::ProfileEvent::process() 3721917SN/A{ 3732680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 3742680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 3752680Sktlim@umich.edu tc->profileSample(); 3761917SN/A } 3772254SN/A 3785606Snate@binkert.org cpu->schedule(this, curTick + interval); 3791917SN/A} 3801917SN/A 3812SN/Avoid 3825704Snate@binkert.orgBaseCPU::postInterrupt(int int_num, int index) 3832SN/A{ 3845647Sgblack@eecs.umich.edu interrupts->post(int_num, index); 3852SN/A} 3862SN/A 3872SN/Avoid 3885704Snate@binkert.orgBaseCPU::clearInterrupt(int int_num, int index) 3892SN/A{ 3905647Sgblack@eecs.umich.edu interrupts->clear(int_num, index); 3912SN/A} 3922SN/A 3932SN/Avoid 3945704Snate@binkert.orgBaseCPU::clearInterrupts() 3952SN/A{ 3965704Snate@binkert.org interrupts->clearAll(); 3972SN/A} 3982SN/A 399921SN/Avoid 400921SN/ABaseCPU::serialize(std::ostream &os) 401921SN/A{ 4024000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 4035647Sgblack@eecs.umich.edu interrupts->serialize(os); 404921SN/A} 405921SN/A 406921SN/Avoid 407921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 408921SN/A{ 4094000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 4105647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 411921SN/A} 412921SN/A 4132SN/A#endif // FULL_SYSTEM 4142SN/A 4151191SN/Avoid 4161191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 4171191SN/A{ 4181191SN/A if (!debugSymbolTable) 4191191SN/A return; 4201191SN/A 4211191SN/A // if pc enters different function, print new function symbol and 4221191SN/A // update saved range. Otherwise do nothing. 4231191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 4241191SN/A string sym_str; 4251191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 4261191SN/A currentFunctionStart, 4271191SN/A currentFunctionEnd); 4281191SN/A 4291191SN/A if (!found) { 4301191SN/A // no symbol found: use addr as label 4311191SN/A sym_str = csprintf("0x%x", pc); 4321191SN/A currentFunctionStart = pc; 4331191SN/A currentFunctionEnd = pc + 1; 4341191SN/A } 4351191SN/A 4361191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 4371191SN/A curTick - functionEntryTick, curTick, sym_str); 4381191SN/A functionEntryTick = curTick; 4391191SN/A } 4401191SN/A} 441