base.cc revision 56 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <string>
30#include <sstream>
31#include <iostream>
32
33#include "cpu/base_cpu.hh"
34#include "base/cprintf.hh"
35#include "cpu/exec_context.hh"
36#include "base/misc.hh"
37#include "sim/sim_events.hh"
38
39using namespace std;
40
41vector<BaseCPU *> BaseCPU::cpuList;
42
43// This variable reflects the max number of threads in any CPU.  Be
44// careful to only use it once all the CPUs that you care about have
45// been initialized
46int maxThreadsPerCPU = 1;
47
48#ifdef FULL_SYSTEM
49BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
50                 Counter max_insts_any_thread,
51                 Counter max_insts_all_threads,
52                 System *_system, int num, Tick freq)
53    : SimObject(_name), number(num), frequency(freq),
54      number_of_threads(_number_of_threads), system(_system)
55#else
56BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
57                 Counter max_insts_any_thread,
58                 Counter max_insts_all_threads)
59    : SimObject(_name), number_of_threads(_number_of_threads)
60#endif
61{
62    // add self to global list of CPUs
63    cpuList.push_back(this);
64
65    if (number_of_threads > maxThreadsPerCPU)
66        maxThreadsPerCPU = number_of_threads;
67
68    // allocate per-thread instruction-based event queues
69    comInsnEventQueue = new (EventQueue *)[number_of_threads];
70    for (int i = 0; i < number_of_threads; ++i)
71        comInsnEventQueue[i] = new EventQueue("instruction-based event queue");
72
73    //
74    // set up instruction-count-based termination events, if any
75    //
76    if (max_insts_any_thread != 0)
77        for (int i = 0; i < number_of_threads; ++i)
78            new SimExitEvent(comInsnEventQueue[i], max_insts_any_thread,
79                "a thread reached the max instruction count");
80
81    if (max_insts_all_threads != 0) {
82        // allocate & initialize shared downcounter: each event will
83        // decrement this when triggered; simulation will terminate
84        // when counter reaches 0
85        int *counter = new int;
86        *counter = number_of_threads;
87        for (int i = 0; i < number_of_threads; ++i)
88            new CountedExitEvent(comInsnEventQueue[i],
89                "all threads reached the max instruction count",
90                max_insts_all_threads, *counter);
91    }
92
93#ifdef FULL_SYSTEM
94    memset(interrupts, 0, sizeof(interrupts));
95    intstatus = 0;
96#endif
97}
98
99void
100BaseCPU::regStats()
101{
102    int size = contexts.size();
103    if (size > 1) {
104        for (int i = 0; i < size; ++i) {
105            stringstream namestr;
106            ccprintf(namestr, "%s.ctx%d", name(), i);
107            contexts[i]->regStats(namestr.str());
108        }
109    } else if (size == 1)
110        contexts[0]->regStats(name());
111}
112
113#ifdef FULL_SYSTEM
114void
115BaseCPU::post_interrupt(int int_num, int index)
116{
117    DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
118
119    if (int_num < 0 || int_num >= NumInterruptLevels)
120        panic("int_num out of bounds\n");
121
122    if (index < 0 || index >= sizeof(uint8_t) * 8)
123        panic("int_num out of bounds\n");
124
125    AlphaISA::check_interrupts = 1;
126    interrupts[int_num] |= 1 << index;
127    intstatus |= (ULL(1) << int_num);
128}
129
130void
131BaseCPU::clear_interrupt(int int_num, int index)
132{
133    DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
134
135    if (int_num < 0 || int_num >= NumInterruptLevels)
136        panic("int_num out of bounds\n");
137
138    if (index < 0 || index >= sizeof(uint8_t) * 8)
139        panic("int_num out of bounds\n");
140
141    interrupts[int_num] &= ~(1 << index);
142    if (interrupts[int_num] == 0)
143        intstatus &= ~(ULL(1) << int_num);
144}
145
146void
147BaseCPU::clear_interrupts()
148{
149    DPRINTF(Interrupt, "Interrupts all cleared\n");
150
151    memset(interrupts, 0, sizeof(interrupts));
152    intstatus = 0;
153}
154
155#endif // FULL_SYSTEM
156
157DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
158