base.cc revision 5217
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431977SN/A#include "cpu/profile.hh" 443144Shsul@eecs.umich.edu#include "sim/sim_exit.hh" 452190SN/A#include "sim/process.hh" 4656SN/A#include "sim/sim_events.hh" 472190SN/A#include "sim/system.hh" 482SN/A 491062SN/A#include "base/trace.hh" 501062SN/A 512359SN/A// Hack 522359SN/A#include "sim/stat_control.hh" 532359SN/A 542SN/Ausing namespace std; 552SN/A 562SN/Avector<BaseCPU *> BaseCPU::cpuList; 572SN/A 582SN/A// This variable reflects the max number of threads in any CPU. Be 592SN/A// careful to only use it once all the CPUs that you care about have 602SN/A// been initialized 612SN/Aint maxThreadsPerCPU = 1; 622SN/A 633126Sktlim@umich.eduCPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, 643126Sktlim@umich.edu BaseCPU *_cpu) 654075Sbinkertn@umich.edu : Event(q, Event::Progress_Event_Pri), interval(ival), 663126Sktlim@umich.edu lastNumInst(0), cpu(_cpu) 673126Sktlim@umich.edu{ 683126Sktlim@umich.edu if (interval) 693126Sktlim@umich.edu schedule(curTick + interval); 703126Sktlim@umich.edu} 713126Sktlim@umich.edu 722356SN/Avoid 732356SN/ACPUProgressEvent::process() 742356SN/A{ 752367SN/A Counter temp = cpu->totalInstructions(); 762356SN/A#ifndef NDEBUG 775100Ssaidi@eecs.umich.edu double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1)); 782367SN/A 792356SN/A DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 802356SN/A cpu->name(), temp - lastNumInst, ipc); 812356SN/A ipc = 0.0; 822367SN/A#else 832367SN/A cprintf("%lli: %s progress event, instructions committed: %lli\n", 842367SN/A curTick, cpu->name(), temp - lastNumInst); 852367SN/A#endif 862356SN/A lastNumInst = temp; 872356SN/A schedule(curTick + interval); 882356SN/A} 892356SN/A 902356SN/Aconst char * 912356SN/ACPUProgressEvent::description() 922356SN/A{ 934873Sstever@eecs.umich.edu return "CPU Progress"; 942356SN/A} 952356SN/A 961858SN/A#if FULL_SYSTEM 971400SN/ABaseCPU::BaseCPU(Params *p) 985034Smilesck@eecs.umich.edu : MemObject(makeParams(p->name)), clock(p->clock), instCnt(0), 993661Srdreslin@umich.edu params(p), number_of_threads(p->numberOfThreads), system(p->system), 1003661Srdreslin@umich.edu phase(p->phase) 1012SN/A#else 1021400SN/ABaseCPU::BaseCPU(Params *p) 1035034Smilesck@eecs.umich.edu : MemObject(makeParams(p->name)), clock(p->clock), params(p), 1043661Srdreslin@umich.edu number_of_threads(p->numberOfThreads), system(p->system), 1053661Srdreslin@umich.edu phase(p->phase) 1062SN/A#endif 1072SN/A{ 1082359SN/A// currentTick = curTick; 1091062SN/A 1102SN/A // add self to global list of CPUs 1112SN/A cpuList.push_back(this); 1122SN/A 1132SN/A if (number_of_threads > maxThreadsPerCPU) 1142SN/A maxThreadsPerCPU = number_of_threads; 1152SN/A 1162SN/A // allocate per-thread instruction-based event queues 1171354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 1182SN/A for (int i = 0; i < number_of_threads; ++i) 119503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 1202SN/A 1212SN/A // 1222SN/A // set up instruction-count-based termination events, if any 1232SN/A // 1241400SN/A if (p->max_insts_any_thread != 0) 1252SN/A for (int i = 0; i < number_of_threads; ++i) 1263144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max instruction count", 1273144Shsul@eecs.umich.edu p->max_insts_any_thread, 0, 1283144Shsul@eecs.umich.edu comInstEventQueue[i]); 1292SN/A 1301400SN/A if (p->max_insts_all_threads != 0) { 1312SN/A // allocate & initialize shared downcounter: each event will 1322SN/A // decrement this when triggered; simulation will terminate 1332SN/A // when counter reaches 0 1342SN/A int *counter = new int; 1352SN/A *counter = number_of_threads; 1362SN/A for (int i = 0; i < number_of_threads; ++i) 137503SN/A new CountedExitEvent(comInstEventQueue[i], 1382SN/A "all threads reached the max instruction count", 1391400SN/A p->max_insts_all_threads, *counter); 1402SN/A } 1412SN/A 142124SN/A // allocate per-thread load-based event queues 1431354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 144124SN/A for (int i = 0; i < number_of_threads; ++i) 145124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 146124SN/A 147124SN/A // 148124SN/A // set up instruction-count-based termination events, if any 149124SN/A // 1501400SN/A if (p->max_loads_any_thread != 0) 151124SN/A for (int i = 0; i < number_of_threads; ++i) 1523144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max load count", 1533144Shsul@eecs.umich.edu p->max_loads_any_thread, 0, 1543144Shsul@eecs.umich.edu comLoadEventQueue[i]); 155124SN/A 1561400SN/A if (p->max_loads_all_threads != 0) { 157124SN/A // allocate & initialize shared downcounter: each event will 158124SN/A // decrement this when triggered; simulation will terminate 159124SN/A // when counter reaches 0 160124SN/A int *counter = new int; 161124SN/A *counter = number_of_threads; 162124SN/A for (int i = 0; i < number_of_threads; ++i) 163124SN/A new CountedExitEvent(comLoadEventQueue[i], 164124SN/A "all threads reached the max load count", 1651400SN/A p->max_loads_all_threads, *counter); 166124SN/A } 167124SN/A 1681191SN/A functionTracingEnabled = false; 1691400SN/A if (p->functionTrace) { 1701388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1711191SN/A currentFunctionStart = currentFunctionEnd = 0; 1721400SN/A functionEntryTick = p->functionTraceStart; 1731191SN/A 1741400SN/A if (p->functionTraceStart == 0) { 1751191SN/A functionTracingEnabled = true; 1761191SN/A } else { 1774471Sstever@eecs.umich.edu new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1784471Sstever@eecs.umich.edu p->functionTraceStart, 1794471Sstever@eecs.umich.edu true); 1801191SN/A } 1811191SN/A } 1821917SN/A#if FULL_SYSTEM 1831917SN/A profileEvent = NULL; 1841917SN/A if (params->profile) 1851917SN/A profileEvent = new ProfileEvent(this, params->profile); 1861917SN/A#endif 1874776Sgblack@eecs.umich.edu tracer = params->tracer; 1882SN/A} 1892SN/A 1901917SN/ABaseCPU::Params::Params() 1911917SN/A{ 1921917SN/A#if FULL_SYSTEM 1931917SN/A profile = false; 1941917SN/A#endif 1952315SN/A checker = NULL; 1964776Sgblack@eecs.umich.edu tracer = NULL; 1971917SN/A} 1981191SN/A 1991191SN/Avoid 2001191SN/ABaseCPU::enableFunctionTrace() 2011191SN/A{ 2021191SN/A functionTracingEnabled = true; 2031191SN/A} 2041191SN/A 2051191SN/ABaseCPU::~BaseCPU() 2061191SN/A{ 2071191SN/A} 2081191SN/A 2091129SN/Avoid 2101129SN/ABaseCPU::init() 2111129SN/A{ 2121400SN/A if (!params->deferRegistration) 2132680Sktlim@umich.edu registerThreadContexts(); 2141129SN/A} 215180SN/A 2162SN/Avoid 2171917SN/ABaseCPU::startup() 2181917SN/A{ 2191917SN/A#if FULL_SYSTEM 2201917SN/A if (!params->deferRegistration && profileEvent) 2211917SN/A profileEvent->schedule(curTick); 2221917SN/A#endif 2232356SN/A 2242356SN/A if (params->progress_interval) { 2254031Sktlim@umich.edu new CPUProgressEvent(&mainEventQueue, 2265100Ssaidi@eecs.umich.edu ticks(params->progress_interval), 2272356SN/A this); 2282356SN/A } 2291917SN/A} 2301917SN/A 2311917SN/A 2321917SN/Avoid 2332SN/ABaseCPU::regStats() 2342SN/A{ 235729SN/A using namespace Stats; 236707SN/A 237707SN/A numCycles 238707SN/A .name(name() + ".numCycles") 239707SN/A .desc("number of cpu cycles simulated") 240707SN/A ; 241707SN/A 2422680Sktlim@umich.edu int size = threadContexts.size(); 2432SN/A if (size > 1) { 2442SN/A for (int i = 0; i < size; ++i) { 2452SN/A stringstream namestr; 2462SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2472680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2482SN/A } 2492SN/A } else if (size == 1) 2502680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2512190SN/A 2522190SN/A#if FULL_SYSTEM 2532190SN/A#endif 2542SN/A} 2552SN/A 2563495Sktlim@umich.eduTick 2573495Sktlim@umich.eduBaseCPU::nextCycle() 2583495Sktlim@umich.edu{ 2593661Srdreslin@umich.edu Tick next_tick = curTick - phase + clock - 1; 2603495Sktlim@umich.edu next_tick -= (next_tick % clock); 2613661Srdreslin@umich.edu next_tick += phase; 2623495Sktlim@umich.edu return next_tick; 2633495Sktlim@umich.edu} 2643495Sktlim@umich.edu 2653495Sktlim@umich.eduTick 2663495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 2673495Sktlim@umich.edu{ 2683495Sktlim@umich.edu Tick next_tick = begin_tick; 2694599Sacolyte@umich.edu if (next_tick % clock != 0) 2704599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 2713661Srdreslin@umich.edu next_tick += phase; 2723495Sktlim@umich.edu 2733495Sktlim@umich.edu assert(next_tick >= curTick); 2743495Sktlim@umich.edu return next_tick; 2753495Sktlim@umich.edu} 276180SN/A 277180SN/Avoid 2782680Sktlim@umich.eduBaseCPU::registerThreadContexts() 279180SN/A{ 2802680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2812680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2822378SN/A 2831858SN/A#if FULL_SYSTEM 2841806SN/A int id = params->cpu_id; 2851806SN/A if (id != -1) 2861806SN/A id += i; 287180SN/A 2882680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 289180SN/A#else 2902680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 291180SN/A#endif 292180SN/A } 293180SN/A} 294180SN/A 295180SN/A 2964000Ssaidi@eecs.umich.eduint 2974000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 2984000Ssaidi@eecs.umich.edu{ 2994000Ssaidi@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3004000Ssaidi@eecs.umich.edu if (tc == threadContexts[i]) 3014000Ssaidi@eecs.umich.edu return i; 3024000Ssaidi@eecs.umich.edu } 3034000Ssaidi@eecs.umich.edu return 0; 3044000Ssaidi@eecs.umich.edu} 3054000Ssaidi@eecs.umich.edu 306180SN/Avoid 3072798Sktlim@umich.eduBaseCPU::switchOut() 308180SN/A{ 3092359SN/A// panic("This CPU doesn't support sampling!"); 3102359SN/A#if FULL_SYSTEM 3112359SN/A if (profileEvent && profileEvent->scheduled()) 3122359SN/A profileEvent->deschedule(); 3132359SN/A#endif 314180SN/A} 315180SN/A 316180SN/Avoid 3174192Sktlim@umich.eduBaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) 318180SN/A{ 3192680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 320180SN/A 3212680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3222680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3232680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 324180SN/A 3252680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3262651Ssaidi@eecs.umich.edu 3272680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3282651Ssaidi@eecs.umich.edu 3292680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 3301858SN/A#if FULL_SYSTEM 3312680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 332180SN/A#else 3332680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 3342680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 335180SN/A#endif 3362359SN/A 3375217Ssaidi@eecs.umich.edu if (DTRACE(Context)) 3385217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 339180SN/A } 340605SN/A 3411858SN/A#if FULL_SYSTEM 3423520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 3432254SN/A 3442680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 3452680Sktlim@umich.edu threadContexts[i]->profileClear(); 3462254SN/A 3474947Snate@binkert.org if (profileEvent) 3484947Snate@binkert.org profileEvent->schedule(curTick); 349612SN/A#endif 3504192Sktlim@umich.edu 3514192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 3524192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 3534192Sktlim@umich.edu // CPU. 3544192Sktlim@umich.edu Port *peer; 3554192Sktlim@umich.edu if (ic->getPeer() == NULL) { 3564192Sktlim@umich.edu peer = oldCPU->getPort("icache_port")->getPeer(); 3574192Sktlim@umich.edu ic->setPeer(peer); 3584192Sktlim@umich.edu } else { 3594192Sktlim@umich.edu peer = ic->getPeer(); 3604192Sktlim@umich.edu } 3614192Sktlim@umich.edu peer->setPeer(ic); 3624192Sktlim@umich.edu 3634192Sktlim@umich.edu if (dc->getPeer() == NULL) { 3644192Sktlim@umich.edu peer = oldCPU->getPort("dcache_port")->getPeer(); 3654192Sktlim@umich.edu dc->setPeer(peer); 3664192Sktlim@umich.edu } else { 3674192Sktlim@umich.edu peer = dc->getPeer(); 3684192Sktlim@umich.edu } 3694192Sktlim@umich.edu peer->setPeer(dc); 370180SN/A} 371180SN/A 372180SN/A 3731858SN/A#if FULL_SYSTEM 3741917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 3751917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 3761917SN/A{ } 3771917SN/A 3781917SN/Avoid 3791917SN/ABaseCPU::ProfileEvent::process() 3801917SN/A{ 3812680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 3822680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 3832680Sktlim@umich.edu tc->profileSample(); 3841917SN/A } 3852254SN/A 3861917SN/A schedule(curTick + interval); 3871917SN/A} 3881917SN/A 3892SN/Avoid 3902SN/ABaseCPU::post_interrupt(int int_num, int index) 3912SN/A{ 3923520Sgblack@eecs.umich.edu interrupts.post(int_num, index); 3932SN/A} 3942SN/A 3952SN/Avoid 3962SN/ABaseCPU::clear_interrupt(int int_num, int index) 3972SN/A{ 3983520Sgblack@eecs.umich.edu interrupts.clear(int_num, index); 3992SN/A} 4002SN/A 4012SN/Avoid 4022SN/ABaseCPU::clear_interrupts() 4032SN/A{ 4043520Sgblack@eecs.umich.edu interrupts.clear_all(); 4052SN/A} 4062SN/A 4074103Ssaidi@eecs.umich.eduuint64_t 4084103Ssaidi@eecs.umich.eduBaseCPU::get_interrupts(int int_num) 4094103Ssaidi@eecs.umich.edu{ 4104103Ssaidi@eecs.umich.edu return interrupts.get_vec(int_num); 4114103Ssaidi@eecs.umich.edu} 412921SN/A 413921SN/Avoid 414921SN/ABaseCPU::serialize(std::ostream &os) 415921SN/A{ 4164000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 4173520Sgblack@eecs.umich.edu interrupts.serialize(os); 418921SN/A} 419921SN/A 420921SN/Avoid 421921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 422921SN/A{ 4234000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 4243520Sgblack@eecs.umich.edu interrupts.unserialize(cp, section); 425921SN/A} 426921SN/A 4272SN/A#endif // FULL_SYSTEM 4282SN/A 4291191SN/Avoid 4301191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 4311191SN/A{ 4321191SN/A if (!debugSymbolTable) 4331191SN/A return; 4341191SN/A 4351191SN/A // if pc enters different function, print new function symbol and 4361191SN/A // update saved range. Otherwise do nothing. 4371191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 4381191SN/A string sym_str; 4391191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 4401191SN/A currentFunctionStart, 4411191SN/A currentFunctionEnd); 4421191SN/A 4431191SN/A if (!found) { 4441191SN/A // no symbol found: use addr as label 4451191SN/A sym_str = csprintf("0x%x", pc); 4461191SN/A currentFunctionStart = pc; 4471191SN/A currentFunctionEnd = pc + 1; 4481191SN/A } 4491191SN/A 4501191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 4511191SN/A curTick - functionEntryTick, curTick, sym_str); 4521191SN/A functionEntryTick = curTick; 4531191SN/A } 4541191SN/A} 455