base.cc revision 4377
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431977SN/A#include "cpu/profile.hh" 443144Shsul@eecs.umich.edu#include "sim/sim_exit.hh" 45161SN/A#include "sim/param.hh" 462190SN/A#include "sim/process.hh" 4756SN/A#include "sim/sim_events.hh" 482190SN/A#include "sim/system.hh" 492SN/A 501062SN/A#include "base/trace.hh" 511062SN/A 522359SN/A// Hack 532359SN/A#include "sim/stat_control.hh" 542359SN/A 552SN/Ausing namespace std; 562SN/A 572SN/Avector<BaseCPU *> BaseCPU::cpuList; 582SN/A 592SN/A// This variable reflects the max number of threads in any CPU. Be 602SN/A// careful to only use it once all the CPUs that you care about have 612SN/A// been initialized 622SN/Aint maxThreadsPerCPU = 1; 632SN/A 643126Sktlim@umich.eduCPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, 653126Sktlim@umich.edu BaseCPU *_cpu) 664075Sbinkertn@umich.edu : Event(q, Event::Progress_Event_Pri), interval(ival), 673126Sktlim@umich.edu lastNumInst(0), cpu(_cpu) 683126Sktlim@umich.edu{ 693126Sktlim@umich.edu if (interval) 703126Sktlim@umich.edu schedule(curTick + interval); 713126Sktlim@umich.edu} 723126Sktlim@umich.edu 732356SN/Avoid 742356SN/ACPUProgressEvent::process() 752356SN/A{ 762367SN/A Counter temp = cpu->totalInstructions(); 772356SN/A#ifndef NDEBUG 782356SN/A double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); 792367SN/A 802356SN/A DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 812356SN/A cpu->name(), temp - lastNumInst, ipc); 822356SN/A ipc = 0.0; 832367SN/A#else 842367SN/A cprintf("%lli: %s progress event, instructions committed: %lli\n", 852367SN/A curTick, cpu->name(), temp - lastNumInst); 862367SN/A#endif 872356SN/A lastNumInst = temp; 882356SN/A schedule(curTick + interval); 892356SN/A} 902356SN/A 912356SN/Aconst char * 922356SN/ACPUProgressEvent::description() 932356SN/A{ 942356SN/A return "CPU Progress event"; 952356SN/A} 962356SN/A 971858SN/A#if FULL_SYSTEM 981400SN/ABaseCPU::BaseCPU(Params *p) 993923Shsul@eecs.umich.edu : MemObject(p->name), clock(p->clock), instCnt(0), 1003661Srdreslin@umich.edu params(p), number_of_threads(p->numberOfThreads), system(p->system), 1013661Srdreslin@umich.edu phase(p->phase) 1022SN/A#else 1031400SN/ABaseCPU::BaseCPU(Params *p) 1042856Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), params(p), 1053661Srdreslin@umich.edu number_of_threads(p->numberOfThreads), system(p->system), 1063661Srdreslin@umich.edu phase(p->phase) 1072SN/A#endif 1082SN/A{ 1092359SN/A// currentTick = curTick; 1102831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 1111062SN/A 1122SN/A // add self to global list of CPUs 1132SN/A cpuList.push_back(this); 1142SN/A 1152831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 1161062SN/A this); 1171062SN/A 1182SN/A if (number_of_threads > maxThreadsPerCPU) 1192SN/A maxThreadsPerCPU = number_of_threads; 1202SN/A 1212SN/A // allocate per-thread instruction-based event queues 1221354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 1232SN/A for (int i = 0; i < number_of_threads; ++i) 124503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 1252SN/A 1262SN/A // 1272SN/A // set up instruction-count-based termination events, if any 1282SN/A // 1291400SN/A if (p->max_insts_any_thread != 0) 1302SN/A for (int i = 0; i < number_of_threads; ++i) 1313144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max instruction count", 1323144Shsul@eecs.umich.edu p->max_insts_any_thread, 0, 1333144Shsul@eecs.umich.edu comInstEventQueue[i]); 1342SN/A 1351400SN/A if (p->max_insts_all_threads != 0) { 1362SN/A // allocate & initialize shared downcounter: each event will 1372SN/A // decrement this when triggered; simulation will terminate 1382SN/A // when counter reaches 0 1392SN/A int *counter = new int; 1402SN/A *counter = number_of_threads; 1412SN/A for (int i = 0; i < number_of_threads; ++i) 142503SN/A new CountedExitEvent(comInstEventQueue[i], 1432SN/A "all threads reached the max instruction count", 1441400SN/A p->max_insts_all_threads, *counter); 1452SN/A } 1462SN/A 147124SN/A // allocate per-thread load-based event queues 1481354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 149124SN/A for (int i = 0; i < number_of_threads; ++i) 150124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 151124SN/A 152124SN/A // 153124SN/A // set up instruction-count-based termination events, if any 154124SN/A // 1551400SN/A if (p->max_loads_any_thread != 0) 156124SN/A for (int i = 0; i < number_of_threads; ++i) 1573144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max load count", 1583144Shsul@eecs.umich.edu p->max_loads_any_thread, 0, 1593144Shsul@eecs.umich.edu comLoadEventQueue[i]); 160124SN/A 1611400SN/A if (p->max_loads_all_threads != 0) { 162124SN/A // allocate & initialize shared downcounter: each event will 163124SN/A // decrement this when triggered; simulation will terminate 164124SN/A // when counter reaches 0 165124SN/A int *counter = new int; 166124SN/A *counter = number_of_threads; 167124SN/A for (int i = 0; i < number_of_threads; ++i) 168124SN/A new CountedExitEvent(comLoadEventQueue[i], 169124SN/A "all threads reached the max load count", 1701400SN/A p->max_loads_all_threads, *counter); 171124SN/A } 172124SN/A 1731191SN/A functionTracingEnabled = false; 1741400SN/A if (p->functionTrace) { 1751388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1761191SN/A currentFunctionStart = currentFunctionEnd = 0; 1771400SN/A functionEntryTick = p->functionTraceStart; 1781191SN/A 1791400SN/A if (p->functionTraceStart == 0) { 1801191SN/A functionTracingEnabled = true; 1811191SN/A } else { 1821191SN/A Event *e = 1831191SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1841191SN/A true); 1851400SN/A e->schedule(p->functionTraceStart); 1861191SN/A } 1871191SN/A } 1881917SN/A#if FULL_SYSTEM 1891917SN/A profileEvent = NULL; 1901917SN/A if (params->profile) 1911917SN/A profileEvent = new ProfileEvent(this, params->profile); 1921917SN/A#endif 1932SN/A} 1942SN/A 1951917SN/ABaseCPU::Params::Params() 1961917SN/A{ 1971917SN/A#if FULL_SYSTEM 1981917SN/A profile = false; 1991917SN/A#endif 2002315SN/A checker = NULL; 2011917SN/A} 2021191SN/A 2031191SN/Avoid 2041191SN/ABaseCPU::enableFunctionTrace() 2051191SN/A{ 2061191SN/A functionTracingEnabled = true; 2071191SN/A} 2081191SN/A 2091191SN/ABaseCPU::~BaseCPU() 2101191SN/A{ 2111191SN/A} 2121191SN/A 2131129SN/Avoid 2141129SN/ABaseCPU::init() 2151129SN/A{ 2161400SN/A if (!params->deferRegistration) 2172680Sktlim@umich.edu registerThreadContexts(); 2181129SN/A} 219180SN/A 2202SN/Avoid 2211917SN/ABaseCPU::startup() 2221917SN/A{ 2231917SN/A#if FULL_SYSTEM 2241917SN/A if (!params->deferRegistration && profileEvent) 2251917SN/A profileEvent->schedule(curTick); 2261917SN/A#endif 2272356SN/A 2282356SN/A if (params->progress_interval) { 2294031Sktlim@umich.edu new CPUProgressEvent(&mainEventQueue, 2304031Sktlim@umich.edu cycles(params->progress_interval), 2312356SN/A this); 2322356SN/A } 2331917SN/A} 2341917SN/A 2351917SN/A 2361917SN/Avoid 2372SN/ABaseCPU::regStats() 2382SN/A{ 239729SN/A using namespace Stats; 240707SN/A 241707SN/A numCycles 242707SN/A .name(name() + ".numCycles") 243707SN/A .desc("number of cpu cycles simulated") 244707SN/A ; 245707SN/A 2462680Sktlim@umich.edu int size = threadContexts.size(); 2472SN/A if (size > 1) { 2482SN/A for (int i = 0; i < size; ++i) { 2492SN/A stringstream namestr; 2502SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2512680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2522SN/A } 2532SN/A } else if (size == 1) 2542680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2552190SN/A 2562190SN/A#if FULL_SYSTEM 2572190SN/A#endif 2582SN/A} 2592SN/A 2603495Sktlim@umich.eduTick 2613495Sktlim@umich.eduBaseCPU::nextCycle() 2623495Sktlim@umich.edu{ 2633661Srdreslin@umich.edu Tick next_tick = curTick - phase + clock - 1; 2643495Sktlim@umich.edu next_tick -= (next_tick % clock); 2653661Srdreslin@umich.edu next_tick += phase; 2663495Sktlim@umich.edu return next_tick; 2673495Sktlim@umich.edu} 2683495Sktlim@umich.edu 2693495Sktlim@umich.eduTick 2703495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 2713495Sktlim@umich.edu{ 2723495Sktlim@umich.edu Tick next_tick = begin_tick; 2733661Srdreslin@umich.edu next_tick -= (next_tick % clock); 2743661Srdreslin@umich.edu next_tick += phase; 2753495Sktlim@umich.edu 2763495Sktlim@umich.edu while (next_tick < curTick) 2773495Sktlim@umich.edu next_tick += clock; 2783495Sktlim@umich.edu 2793495Sktlim@umich.edu assert(next_tick >= curTick); 2803495Sktlim@umich.edu return next_tick; 2813495Sktlim@umich.edu} 282180SN/A 283180SN/Avoid 2842680Sktlim@umich.eduBaseCPU::registerThreadContexts() 285180SN/A{ 2862680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2872680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2882378SN/A 2891858SN/A#if FULL_SYSTEM 2901806SN/A int id = params->cpu_id; 2911806SN/A if (id != -1) 2921806SN/A id += i; 293180SN/A 2942680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 295180SN/A#else 2962680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 297180SN/A#endif 298180SN/A } 299180SN/A} 300180SN/A 301180SN/A 3024000Ssaidi@eecs.umich.eduint 3034000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3044000Ssaidi@eecs.umich.edu{ 3054000Ssaidi@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3064000Ssaidi@eecs.umich.edu if (tc == threadContexts[i]) 3074000Ssaidi@eecs.umich.edu return i; 3084000Ssaidi@eecs.umich.edu } 3094000Ssaidi@eecs.umich.edu return 0; 3104000Ssaidi@eecs.umich.edu} 3114000Ssaidi@eecs.umich.edu 312180SN/Avoid 3132798Sktlim@umich.eduBaseCPU::switchOut() 314180SN/A{ 3152359SN/A// panic("This CPU doesn't support sampling!"); 3162359SN/A#if FULL_SYSTEM 3172359SN/A if (profileEvent && profileEvent->scheduled()) 3182359SN/A profileEvent->deschedule(); 3192359SN/A#endif 320180SN/A} 321180SN/A 322180SN/Avoid 3234192Sktlim@umich.eduBaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) 324180SN/A{ 3252680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 326180SN/A 3272680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 3282680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3292680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 330180SN/A 3312680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3322651Ssaidi@eecs.umich.edu 3332680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3342651Ssaidi@eecs.umich.edu 3352680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 3361858SN/A#if FULL_SYSTEM 3372680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 338180SN/A#else 3392680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 3402680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 341180SN/A#endif 3422359SN/A 3432359SN/A// TheISA::compareXCs(oldXC, newXC); 344180SN/A } 345605SN/A 3461858SN/A#if FULL_SYSTEM 3473520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 3482254SN/A 3492680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 3502680Sktlim@umich.edu threadContexts[i]->profileClear(); 3512254SN/A 3522359SN/A // The Sampler must take care of this! 3532359SN/A// if (profileEvent) 3542359SN/A// profileEvent->schedule(curTick); 355612SN/A#endif 3564192Sktlim@umich.edu 3574192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 3584192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 3594192Sktlim@umich.edu // CPU. 3604192Sktlim@umich.edu Port *peer; 3614192Sktlim@umich.edu if (ic->getPeer() == NULL) { 3624192Sktlim@umich.edu peer = oldCPU->getPort("icache_port")->getPeer(); 3634192Sktlim@umich.edu ic->setPeer(peer); 3644192Sktlim@umich.edu } else { 3654192Sktlim@umich.edu peer = ic->getPeer(); 3664192Sktlim@umich.edu } 3674192Sktlim@umich.edu peer->setPeer(ic); 3684192Sktlim@umich.edu 3694192Sktlim@umich.edu if (dc->getPeer() == NULL) { 3704192Sktlim@umich.edu peer = oldCPU->getPort("dcache_port")->getPeer(); 3714192Sktlim@umich.edu dc->setPeer(peer); 3724192Sktlim@umich.edu } else { 3734192Sktlim@umich.edu peer = dc->getPeer(); 3744192Sktlim@umich.edu } 3754192Sktlim@umich.edu peer->setPeer(dc); 376180SN/A} 377180SN/A 378180SN/A 3791858SN/A#if FULL_SYSTEM 3801917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 3811917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 3821917SN/A{ } 3831917SN/A 3841917SN/Avoid 3851917SN/ABaseCPU::ProfileEvent::process() 3861917SN/A{ 3872680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 3882680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 3892680Sktlim@umich.edu tc->profileSample(); 3901917SN/A } 3912254SN/A 3921917SN/A schedule(curTick + interval); 3931917SN/A} 3941917SN/A 3952SN/Avoid 3962SN/ABaseCPU::post_interrupt(int int_num, int index) 3972SN/A{ 3983520Sgblack@eecs.umich.edu interrupts.post(int_num, index); 3992SN/A} 4002SN/A 4012SN/Avoid 4022SN/ABaseCPU::clear_interrupt(int int_num, int index) 4032SN/A{ 4043520Sgblack@eecs.umich.edu interrupts.clear(int_num, index); 4052SN/A} 4062SN/A 4072SN/Avoid 4082SN/ABaseCPU::clear_interrupts() 4092SN/A{ 4103520Sgblack@eecs.umich.edu interrupts.clear_all(); 4112SN/A} 4122SN/A 4134103Ssaidi@eecs.umich.eduuint64_t 4144103Ssaidi@eecs.umich.eduBaseCPU::get_interrupts(int int_num) 4154103Ssaidi@eecs.umich.edu{ 4164103Ssaidi@eecs.umich.edu return interrupts.get_vec(int_num); 4174103Ssaidi@eecs.umich.edu} 418921SN/A 419921SN/Avoid 420921SN/ABaseCPU::serialize(std::ostream &os) 421921SN/A{ 4224000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 4233520Sgblack@eecs.umich.edu interrupts.serialize(os); 424921SN/A} 425921SN/A 426921SN/Avoid 427921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 428921SN/A{ 4294000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 4303520Sgblack@eecs.umich.edu interrupts.unserialize(cp, section); 431921SN/A} 432921SN/A 4332SN/A#endif // FULL_SYSTEM 4342SN/A 4351191SN/Avoid 4361191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 4371191SN/A{ 4381191SN/A if (!debugSymbolTable) 4391191SN/A return; 4401191SN/A 4411191SN/A // if pc enters different function, print new function symbol and 4421191SN/A // update saved range. Otherwise do nothing. 4431191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 4441191SN/A string sym_str; 4451191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 4461191SN/A currentFunctionStart, 4471191SN/A currentFunctionEnd); 4481191SN/A 4491191SN/A if (!found) { 4501191SN/A // no symbol found: use addr as label 4511191SN/A sym_str = csprintf("0x%x", pc); 4521191SN/A currentFunctionStart = pc; 4531191SN/A currentFunctionEnd = pc + 1; 4541191SN/A } 4551191SN/A 4561191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 4571191SN/A curTick - functionEntryTick, curTick, sym_str); 4581191SN/A functionEntryTick = curTick; 4591191SN/A } 4601191SN/A} 4611191SN/A 4621191SN/A 4632SN/ADEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 464