base.cc revision 3520
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431977SN/A#include "cpu/profile.hh" 443144Shsul@eecs.umich.edu#include "sim/sim_exit.hh" 45161SN/A#include "sim/param.hh" 462190SN/A#include "sim/process.hh" 4756SN/A#include "sim/sim_events.hh" 482190SN/A#include "sim/system.hh" 492SN/A 501062SN/A#include "base/trace.hh" 511062SN/A 522359SN/A// Hack 532359SN/A#include "sim/stat_control.hh" 542359SN/A 552SN/Ausing namespace std; 562SN/A 572SN/Avector<BaseCPU *> BaseCPU::cpuList; 582SN/A 592SN/A// This variable reflects the max number of threads in any CPU. Be 602SN/A// careful to only use it once all the CPUs that you care about have 612SN/A// been initialized 622SN/Aint maxThreadsPerCPU = 1; 632SN/A 643126Sktlim@umich.eduCPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, 653126Sktlim@umich.edu BaseCPU *_cpu) 663126Sktlim@umich.edu : Event(q, Event::Stat_Event_Pri), interval(ival), 673126Sktlim@umich.edu lastNumInst(0), cpu(_cpu) 683126Sktlim@umich.edu{ 693126Sktlim@umich.edu if (interval) 703126Sktlim@umich.edu schedule(curTick + interval); 713126Sktlim@umich.edu} 723126Sktlim@umich.edu 732356SN/Avoid 742356SN/ACPUProgressEvent::process() 752356SN/A{ 762367SN/A Counter temp = cpu->totalInstructions(); 772356SN/A#ifndef NDEBUG 782356SN/A double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); 792367SN/A 802356SN/A DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 812356SN/A cpu->name(), temp - lastNumInst, ipc); 822356SN/A ipc = 0.0; 832367SN/A#else 842367SN/A cprintf("%lli: %s progress event, instructions committed: %lli\n", 852367SN/A curTick, cpu->name(), temp - lastNumInst); 862367SN/A#endif 872356SN/A lastNumInst = temp; 882356SN/A schedule(curTick + interval); 892356SN/A} 902356SN/A 912356SN/Aconst char * 922356SN/ACPUProgressEvent::description() 932356SN/A{ 942356SN/A return "CPU Progress event"; 952356SN/A} 962356SN/A 971858SN/A#if FULL_SYSTEM 981400SN/ABaseCPU::BaseCPU(Params *p) 992881Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), checkInterrupts(true), 1001400SN/A params(p), number_of_threads(p->numberOfThreads), system(p->system) 1012SN/A#else 1021400SN/ABaseCPU::BaseCPU(Params *p) 1032856Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), params(p), 1042378SN/A number_of_threads(p->numberOfThreads), system(p->system) 1052SN/A#endif 1062SN/A{ 1072359SN/A// currentTick = curTick; 1082831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 1091062SN/A 1102SN/A // add self to global list of CPUs 1112SN/A cpuList.push_back(this); 1122SN/A 1132831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 1141062SN/A this); 1151062SN/A 1162SN/A if (number_of_threads > maxThreadsPerCPU) 1172SN/A maxThreadsPerCPU = number_of_threads; 1182SN/A 1192SN/A // allocate per-thread instruction-based event queues 1201354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 1212SN/A for (int i = 0; i < number_of_threads; ++i) 122503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 1232SN/A 1242SN/A // 1252SN/A // set up instruction-count-based termination events, if any 1262SN/A // 1271400SN/A if (p->max_insts_any_thread != 0) 1282SN/A for (int i = 0; i < number_of_threads; ++i) 1293144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max instruction count", 1303144Shsul@eecs.umich.edu p->max_insts_any_thread, 0, 1313144Shsul@eecs.umich.edu comInstEventQueue[i]); 1322SN/A 1331400SN/A if (p->max_insts_all_threads != 0) { 1342SN/A // allocate & initialize shared downcounter: each event will 1352SN/A // decrement this when triggered; simulation will terminate 1362SN/A // when counter reaches 0 1372SN/A int *counter = new int; 1382SN/A *counter = number_of_threads; 1392SN/A for (int i = 0; i < number_of_threads; ++i) 140503SN/A new CountedExitEvent(comInstEventQueue[i], 1412SN/A "all threads reached the max instruction count", 1421400SN/A p->max_insts_all_threads, *counter); 1432SN/A } 1442SN/A 145124SN/A // allocate per-thread load-based event queues 1461354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 147124SN/A for (int i = 0; i < number_of_threads; ++i) 148124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 149124SN/A 150124SN/A // 151124SN/A // set up instruction-count-based termination events, if any 152124SN/A // 1531400SN/A if (p->max_loads_any_thread != 0) 154124SN/A for (int i = 0; i < number_of_threads; ++i) 1553144Shsul@eecs.umich.edu schedExitSimLoop("a thread reached the max load count", 1563144Shsul@eecs.umich.edu p->max_loads_any_thread, 0, 1573144Shsul@eecs.umich.edu comLoadEventQueue[i]); 158124SN/A 1591400SN/A if (p->max_loads_all_threads != 0) { 160124SN/A // allocate & initialize shared downcounter: each event will 161124SN/A // decrement this when triggered; simulation will terminate 162124SN/A // when counter reaches 0 163124SN/A int *counter = new int; 164124SN/A *counter = number_of_threads; 165124SN/A for (int i = 0; i < number_of_threads; ++i) 166124SN/A new CountedExitEvent(comLoadEventQueue[i], 167124SN/A "all threads reached the max load count", 1681400SN/A p->max_loads_all_threads, *counter); 169124SN/A } 170124SN/A 1711191SN/A functionTracingEnabled = false; 1721400SN/A if (p->functionTrace) { 1731388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1741191SN/A currentFunctionStart = currentFunctionEnd = 0; 1751400SN/A functionEntryTick = p->functionTraceStart; 1761191SN/A 1771400SN/A if (p->functionTraceStart == 0) { 1781191SN/A functionTracingEnabled = true; 1791191SN/A } else { 1801191SN/A Event *e = 1811191SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1821191SN/A true); 1831400SN/A e->schedule(p->functionTraceStart); 1841191SN/A } 1851191SN/A } 1861917SN/A#if FULL_SYSTEM 1871917SN/A profileEvent = NULL; 1881917SN/A if (params->profile) 1891917SN/A profileEvent = new ProfileEvent(this, params->profile); 1901917SN/A#endif 1912SN/A} 1922SN/A 1931917SN/ABaseCPU::Params::Params() 1941917SN/A{ 1951917SN/A#if FULL_SYSTEM 1961917SN/A profile = false; 1971917SN/A#endif 1982315SN/A checker = NULL; 1991917SN/A} 2001191SN/A 2011191SN/Avoid 2021191SN/ABaseCPU::enableFunctionTrace() 2031191SN/A{ 2041191SN/A functionTracingEnabled = true; 2051191SN/A} 2061191SN/A 2071191SN/ABaseCPU::~BaseCPU() 2081191SN/A{ 2091191SN/A} 2101191SN/A 2111129SN/Avoid 2121129SN/ABaseCPU::init() 2131129SN/A{ 2141400SN/A if (!params->deferRegistration) 2152680Sktlim@umich.edu registerThreadContexts(); 2161129SN/A} 217180SN/A 2182SN/Avoid 2191917SN/ABaseCPU::startup() 2201917SN/A{ 2211917SN/A#if FULL_SYSTEM 2221917SN/A if (!params->deferRegistration && profileEvent) 2231917SN/A profileEvent->schedule(curTick); 2241917SN/A#endif 2252356SN/A 2262356SN/A if (params->progress_interval) { 2272356SN/A new CPUProgressEvent(&mainEventQueue, params->progress_interval, 2282356SN/A this); 2292356SN/A } 2301917SN/A} 2311917SN/A 2321917SN/A 2331917SN/Avoid 2342SN/ABaseCPU::regStats() 2352SN/A{ 236729SN/A using namespace Stats; 237707SN/A 238707SN/A numCycles 239707SN/A .name(name() + ".numCycles") 240707SN/A .desc("number of cpu cycles simulated") 241707SN/A ; 242707SN/A 2432680Sktlim@umich.edu int size = threadContexts.size(); 2442SN/A if (size > 1) { 2452SN/A for (int i = 0; i < size; ++i) { 2462SN/A stringstream namestr; 2472SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2482680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2492SN/A } 2502SN/A } else if (size == 1) 2512680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2522190SN/A 2532190SN/A#if FULL_SYSTEM 2542190SN/A#endif 2552SN/A} 2562SN/A 257180SN/A 258180SN/Avoid 2592680Sktlim@umich.eduBaseCPU::registerThreadContexts() 260180SN/A{ 2612680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2622680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2632378SN/A 2641858SN/A#if FULL_SYSTEM 2651806SN/A int id = params->cpu_id; 2661806SN/A if (id != -1) 2671806SN/A id += i; 268180SN/A 2692680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 270180SN/A#else 2712680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 272180SN/A#endif 273180SN/A } 274180SN/A} 275180SN/A 276180SN/A 277180SN/Avoid 2782798Sktlim@umich.eduBaseCPU::switchOut() 279180SN/A{ 2802359SN/A// panic("This CPU doesn't support sampling!"); 2812359SN/A#if FULL_SYSTEM 2822359SN/A if (profileEvent && profileEvent->scheduled()) 2832359SN/A profileEvent->deschedule(); 2842359SN/A#endif 285180SN/A} 286180SN/A 287180SN/Avoid 288180SN/ABaseCPU::takeOverFrom(BaseCPU *oldCPU) 289180SN/A{ 2902680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 291180SN/A 2922680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2932680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 2942680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 295180SN/A 2962680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 2972651Ssaidi@eecs.umich.edu 2982680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 2992651Ssaidi@eecs.umich.edu 3002680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 3011858SN/A#if FULL_SYSTEM 3022680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 303180SN/A#else 3042680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 3052680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 306180SN/A#endif 3072359SN/A 3082359SN/A// TheISA::compareXCs(oldXC, newXC); 309180SN/A } 310605SN/A 3111858SN/A#if FULL_SYSTEM 3123520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 3132359SN/A checkInterrupts = oldCPU->checkInterrupts; 3142254SN/A 3152680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 3162680Sktlim@umich.edu threadContexts[i]->profileClear(); 3172254SN/A 3182359SN/A // The Sampler must take care of this! 3192359SN/A// if (profileEvent) 3202359SN/A// profileEvent->schedule(curTick); 321612SN/A#endif 322180SN/A} 323180SN/A 324180SN/A 3251858SN/A#if FULL_SYSTEM 3261917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 3271917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 3281917SN/A{ } 3291917SN/A 3301917SN/Avoid 3311917SN/ABaseCPU::ProfileEvent::process() 3321917SN/A{ 3332680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 3342680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 3352680Sktlim@umich.edu tc->profileSample(); 3361917SN/A } 3372254SN/A 3381917SN/A schedule(curTick + interval); 3391917SN/A} 3401917SN/A 3412SN/Avoid 3422SN/ABaseCPU::post_interrupt(int int_num, int index) 3432SN/A{ 3441133SN/A checkInterrupts = true; 3453520Sgblack@eecs.umich.edu interrupts.post(int_num, index); 3462SN/A} 3472SN/A 3482SN/Avoid 3492SN/ABaseCPU::clear_interrupt(int int_num, int index) 3502SN/A{ 3513520Sgblack@eecs.umich.edu interrupts.clear(int_num, index); 3522SN/A} 3532SN/A 3542SN/Avoid 3552SN/ABaseCPU::clear_interrupts() 3562SN/A{ 3573520Sgblack@eecs.umich.edu interrupts.clear_all(); 3582SN/A} 3592SN/A 360921SN/A 361921SN/Avoid 362921SN/ABaseCPU::serialize(std::ostream &os) 363921SN/A{ 3643520Sgblack@eecs.umich.edu interrupts.serialize(os); 365921SN/A} 366921SN/A 367921SN/Avoid 368921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 369921SN/A{ 3703520Sgblack@eecs.umich.edu interrupts.unserialize(cp, section); 371921SN/A} 372921SN/A 3732SN/A#endif // FULL_SYSTEM 3742SN/A 3751191SN/Avoid 3761191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 3771191SN/A{ 3781191SN/A if (!debugSymbolTable) 3791191SN/A return; 3801191SN/A 3811191SN/A // if pc enters different function, print new function symbol and 3821191SN/A // update saved range. Otherwise do nothing. 3831191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 3841191SN/A string sym_str; 3851191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 3861191SN/A currentFunctionStart, 3871191SN/A currentFunctionEnd); 3881191SN/A 3891191SN/A if (!found) { 3901191SN/A // no symbol found: use addr as label 3911191SN/A sym_str = csprintf("0x%x", pc); 3921191SN/A currentFunctionStart = pc; 3931191SN/A currentFunctionEnd = pc + 1; 3941191SN/A } 3951191SN/A 3961191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 3971191SN/A curTick - functionEntryTick, curTick, sym_str); 3981191SN/A functionEntryTick = curTick; 3991191SN/A } 4001191SN/A} 4011191SN/A 4021191SN/A 4032SN/ADEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 404