base.cc revision 2915
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431977SN/A#include "cpu/profile.hh" 44161SN/A#include "sim/param.hh" 452190SN/A#include "sim/process.hh" 4656SN/A#include "sim/sim_events.hh" 472190SN/A#include "sim/system.hh" 482SN/A 491062SN/A#include "base/trace.hh" 501062SN/A 512SN/Ausing namespace std; 522SN/A 532SN/Avector<BaseCPU *> BaseCPU::cpuList; 542SN/A 552SN/A// This variable reflects the max number of threads in any CPU. Be 562SN/A// careful to only use it once all the CPUs that you care about have 572SN/A// been initialized 582SN/Aint maxThreadsPerCPU = 1; 592SN/A 601858SN/A#if FULL_SYSTEM 611400SN/ABaseCPU::BaseCPU(Params *p) 622881Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), checkInterrupts(true), 631400SN/A params(p), number_of_threads(p->numberOfThreads), system(p->system) 642SN/A#else 651400SN/ABaseCPU::BaseCPU(Params *p) 662856Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), params(p), 672378SN/A number_of_threads(p->numberOfThreads), system(p->system) 682SN/A#endif 692SN/A{ 702831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 711062SN/A 722SN/A // add self to global list of CPUs 732SN/A cpuList.push_back(this); 742SN/A 752831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 761062SN/A this); 771062SN/A 782SN/A if (number_of_threads > maxThreadsPerCPU) 792SN/A maxThreadsPerCPU = number_of_threads; 802SN/A 812SN/A // allocate per-thread instruction-based event queues 821354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 832SN/A for (int i = 0; i < number_of_threads; ++i) 84503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 852SN/A 862SN/A // 872SN/A // set up instruction-count-based termination events, if any 882SN/A // 891400SN/A if (p->max_insts_any_thread != 0) 902SN/A for (int i = 0; i < number_of_threads; ++i) 912667Sstever@eecs.umich.edu new SimLoopExitEvent(comInstEventQueue[i], p->max_insts_any_thread, 922667Sstever@eecs.umich.edu "a thread reached the max instruction count"); 932SN/A 941400SN/A if (p->max_insts_all_threads != 0) { 952SN/A // allocate & initialize shared downcounter: each event will 962SN/A // decrement this when triggered; simulation will terminate 972SN/A // when counter reaches 0 982SN/A int *counter = new int; 992SN/A *counter = number_of_threads; 1002SN/A for (int i = 0; i < number_of_threads; ++i) 101503SN/A new CountedExitEvent(comInstEventQueue[i], 1022SN/A "all threads reached the max instruction count", 1031400SN/A p->max_insts_all_threads, *counter); 1042SN/A } 1052SN/A 106124SN/A // allocate per-thread load-based event queues 1071354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 108124SN/A for (int i = 0; i < number_of_threads; ++i) 109124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 110124SN/A 111124SN/A // 112124SN/A // set up instruction-count-based termination events, if any 113124SN/A // 1141400SN/A if (p->max_loads_any_thread != 0) 115124SN/A for (int i = 0; i < number_of_threads; ++i) 1162667Sstever@eecs.umich.edu new SimLoopExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, 1172667Sstever@eecs.umich.edu "a thread reached the max load count"); 118124SN/A 1191400SN/A if (p->max_loads_all_threads != 0) { 120124SN/A // allocate & initialize shared downcounter: each event will 121124SN/A // decrement this when triggered; simulation will terminate 122124SN/A // when counter reaches 0 123124SN/A int *counter = new int; 124124SN/A *counter = number_of_threads; 125124SN/A for (int i = 0; i < number_of_threads; ++i) 126124SN/A new CountedExitEvent(comLoadEventQueue[i], 127124SN/A "all threads reached the max load count", 1281400SN/A p->max_loads_all_threads, *counter); 129124SN/A } 130124SN/A 1311858SN/A#if FULL_SYSTEM 1322SN/A memset(interrupts, 0, sizeof(interrupts)); 1332SN/A intstatus = 0; 1342SN/A#endif 1351191SN/A 1361191SN/A functionTracingEnabled = false; 1371400SN/A if (p->functionTrace) { 1381388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1391191SN/A currentFunctionStart = currentFunctionEnd = 0; 1401400SN/A functionEntryTick = p->functionTraceStart; 1411191SN/A 1421400SN/A if (p->functionTraceStart == 0) { 1431191SN/A functionTracingEnabled = true; 1441191SN/A } else { 1451191SN/A Event *e = 1461191SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1471191SN/A true); 1481400SN/A e->schedule(p->functionTraceStart); 1491191SN/A } 1501191SN/A } 1511917SN/A#if FULL_SYSTEM 1521917SN/A profileEvent = NULL; 1531917SN/A if (params->profile) 1541917SN/A profileEvent = new ProfileEvent(this, params->profile); 1551917SN/A#endif 1562190SN/A 1572SN/A} 1582SN/A 1591917SN/ABaseCPU::Params::Params() 1601917SN/A{ 1611917SN/A#if FULL_SYSTEM 1621917SN/A profile = false; 1631917SN/A#endif 1642315SN/A checker = NULL; 1651917SN/A} 1661191SN/A 1671191SN/Avoid 1681191SN/ABaseCPU::enableFunctionTrace() 1691191SN/A{ 1701191SN/A functionTracingEnabled = true; 1711191SN/A} 1721191SN/A 1731191SN/ABaseCPU::~BaseCPU() 1741191SN/A{ 1751191SN/A} 1761191SN/A 1771129SN/Avoid 1781129SN/ABaseCPU::init() 1791129SN/A{ 1801400SN/A if (!params->deferRegistration) 1812680Sktlim@umich.edu registerThreadContexts(); 1821129SN/A} 183180SN/A 1842SN/Avoid 1851917SN/ABaseCPU::startup() 1861917SN/A{ 1871917SN/A#if FULL_SYSTEM 1881917SN/A if (!params->deferRegistration && profileEvent) 1891917SN/A profileEvent->schedule(curTick); 1901917SN/A#endif 1911917SN/A} 1921917SN/A 1931917SN/A 1941917SN/Avoid 1952SN/ABaseCPU::regStats() 1962SN/A{ 197729SN/A using namespace Stats; 198707SN/A 199707SN/A numCycles 200707SN/A .name(name() + ".numCycles") 201707SN/A .desc("number of cpu cycles simulated") 202707SN/A ; 203707SN/A 2042680Sktlim@umich.edu int size = threadContexts.size(); 2052SN/A if (size > 1) { 2062SN/A for (int i = 0; i < size; ++i) { 2072SN/A stringstream namestr; 2082SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2092680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2102SN/A } 2112SN/A } else if (size == 1) 2122680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2132190SN/A 2142190SN/A#if FULL_SYSTEM 2152190SN/A#endif 2162SN/A} 2172SN/A 218180SN/A 219180SN/Avoid 2202680Sktlim@umich.eduBaseCPU::registerThreadContexts() 221180SN/A{ 2222680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2232680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2242378SN/A 2251858SN/A#if FULL_SYSTEM 2261806SN/A int id = params->cpu_id; 2271806SN/A if (id != -1) 2281806SN/A id += i; 229180SN/A 2302680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 231180SN/A#else 2322680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 233180SN/A#endif 234180SN/A } 235180SN/A} 236180SN/A 237180SN/A 238180SN/Avoid 2392798Sktlim@umich.eduBaseCPU::switchOut() 240180SN/A{ 2411545SN/A panic("This CPU doesn't support sampling!"); 242180SN/A} 243180SN/A 244180SN/Avoid 245180SN/ABaseCPU::takeOverFrom(BaseCPU *oldCPU) 246180SN/A{ 2472680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 248180SN/A 2492680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2502680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 2512680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 252180SN/A 2532680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 2542651Ssaidi@eecs.umich.edu 2552680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 2562651Ssaidi@eecs.umich.edu 2572680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 2581858SN/A#if FULL_SYSTEM 2592680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 260180SN/A#else 2612680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 2622680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 263180SN/A#endif 264180SN/A } 265605SN/A 2661858SN/A#if FULL_SYSTEM 2672107SN/A for (int i = 0; i < TheISA::NumInterruptLevels; ++i) 268605SN/A interrupts[i] = oldCPU->interrupts[i]; 269605SN/A intstatus = oldCPU->intstatus; 2702254SN/A 2712680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 2722680Sktlim@umich.edu threadContexts[i]->profileClear(); 2732254SN/A 2741917SN/A if (profileEvent) 2751917SN/A profileEvent->schedule(curTick); 276612SN/A#endif 277180SN/A} 278180SN/A 279180SN/A 2801858SN/A#if FULL_SYSTEM 2811917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 2821917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 2831917SN/A{ } 2841917SN/A 2851917SN/Avoid 2861917SN/ABaseCPU::ProfileEvent::process() 2871917SN/A{ 2882680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 2892680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 2902680Sktlim@umich.edu tc->profileSample(); 2911917SN/A } 2922254SN/A 2931917SN/A schedule(curTick + interval); 2941917SN/A} 2951917SN/A 2962SN/Avoid 2972SN/ABaseCPU::post_interrupt(int int_num, int index) 2982SN/A{ 2992SN/A DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 3002SN/A 3012107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3022SN/A panic("int_num out of bounds\n"); 3032SN/A 304822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3052SN/A panic("int_num out of bounds\n"); 3062SN/A 3071133SN/A checkInterrupts = true; 3082SN/A interrupts[int_num] |= 1 << index; 3092SN/A intstatus |= (ULL(1) << int_num); 3102SN/A} 3112SN/A 3122SN/Avoid 3132SN/ABaseCPU::clear_interrupt(int int_num, int index) 3142SN/A{ 3152SN/A DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 3162SN/A 3172107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3182SN/A panic("int_num out of bounds\n"); 3192SN/A 320822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3212SN/A panic("int_num out of bounds\n"); 3222SN/A 3232SN/A interrupts[int_num] &= ~(1 << index); 3242SN/A if (interrupts[int_num] == 0) 3252SN/A intstatus &= ~(ULL(1) << int_num); 3262SN/A} 3272SN/A 3282SN/Avoid 3292SN/ABaseCPU::clear_interrupts() 3302SN/A{ 3312SN/A DPRINTF(Interrupt, "Interrupts all cleared\n"); 3322SN/A 3332SN/A memset(interrupts, 0, sizeof(interrupts)); 3342SN/A intstatus = 0; 3352SN/A} 3362SN/A 337921SN/A 338921SN/Avoid 339921SN/ABaseCPU::serialize(std::ostream &os) 340921SN/A{ 3412107SN/A SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 342921SN/A SERIALIZE_SCALAR(intstatus); 343921SN/A} 344921SN/A 345921SN/Avoid 346921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 347921SN/A{ 3482107SN/A UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 349921SN/A UNSERIALIZE_SCALAR(intstatus); 350921SN/A} 351921SN/A 3522SN/A#endif // FULL_SYSTEM 3532SN/A 3541191SN/Avoid 3551191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 3561191SN/A{ 3571191SN/A if (!debugSymbolTable) 3581191SN/A return; 3591191SN/A 3601191SN/A // if pc enters different function, print new function symbol and 3611191SN/A // update saved range. Otherwise do nothing. 3621191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 3631191SN/A string sym_str; 3641191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 3651191SN/A currentFunctionStart, 3661191SN/A currentFunctionEnd); 3671191SN/A 3681191SN/A if (!found) { 3691191SN/A // no symbol found: use addr as label 3701191SN/A sym_str = csprintf("0x%x", pc); 3711191SN/A currentFunctionStart = pc; 3721191SN/A currentFunctionEnd = pc + 1; 3731191SN/A } 3741191SN/A 3751191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 3761191SN/A curTick - functionEntryTick, curTick, sym_str); 3771191SN/A functionEntryTick = curTick; 3781191SN/A } 3791191SN/A} 3801191SN/A 3811191SN/A 3822SN/ADEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 383