base.cc revision 12680
12SN/A/* 212276Sanouk.vanlaer@arm.com * Copyright (c) 2011-2012,2016-2017 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 4811793Sbrandon.potter@amd.com#include "cpu/base.hh" 4911793Sbrandon.potter@amd.com 501388SN/A#include <iostream> 518229Snate@binkert.org#include <sstream> 522SN/A#include <string> 532SN/A 5412406Sgabeblack@google.com#include "arch/generic/tlb.hh" 5511793Sbrandon.potter@amd.com#include "base/cprintf.hh" 568229Snate@binkert.org#include "base/loader/symtab.hh" 5712334Sgabeblack@google.com#include "base/logging.hh" 581388SN/A#include "base/output.hh" 595529Snate@binkert.org#include "base/trace.hh" 6010529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 612651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 628229Snate@binkert.org#include "cpu/profile.hh" 632680Sktlim@umich.edu#include "cpu/thread_context.hh" 6410529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 658232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6610529Smorr@cs.wisc.edu#include "mem/page_table.hh" 675529Snate@binkert.org#include "params/BaseCPU.hh" 6811526Sdavid.guillen@arm.com#include "sim/clocked_object.hh" 698779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 702190SN/A#include "sim/process.hh" 7156SN/A#include "sim/sim_events.hh" 728229Snate@binkert.org#include "sim/sim_exit.hh" 732190SN/A#include "sim/system.hh" 742SN/A 752359SN/A// Hack 762359SN/A#include "sim/stat_control.hh" 772359SN/A 782SN/Ausing namespace std; 792SN/A 802SN/Avector<BaseCPU *> BaseCPU::cpuList; 812SN/A 822SN/A// This variable reflects the max number of threads in any CPU. Be 832SN/A// careful to only use it once all the CPUs that you care about have 842SN/A// been initialized 852SN/Aint maxThreadsPerCPU = 1; 862SN/A 875606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 886144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 896144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 903126Sktlim@umich.edu{ 916144Sksewell@umich.edu if (_interval) 927823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 933126Sktlim@umich.edu} 943126Sktlim@umich.edu 952356SN/Avoid 962356SN/ACPUProgressEvent::process() 972356SN/A{ 988834Satgutier@umich.edu Counter temp = cpu->totalOps(); 9910786Smalek.musleh@gmail.com 10010786Smalek.musleh@gmail.com if (_repeatEvent) 10110786Smalek.musleh@gmail.com cpu->schedule(this, curTick() + _interval); 10210786Smalek.musleh@gmail.com 10311321Ssteve.reinhardt@amd.com if (cpu->switchedOut()) { 10410786Smalek.musleh@gmail.com return; 10510786Smalek.musleh@gmail.com } 10610786Smalek.musleh@gmail.com 1072356SN/A#ifndef NDEBUG 1089179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 1092367SN/A 1106144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1116144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1126144Sksewell@umich.edu ipc); 1132356SN/A ipc = 0.0; 1142367SN/A#else 1156144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1167823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1176144Sksewell@umich.edu temp - lastNumInst); 1182367SN/A#endif 1192356SN/A lastNumInst = temp; 1202356SN/A} 1212356SN/A 1222356SN/Aconst char * 1235336Shines@cs.fsu.eduCPUProgressEvent::description() const 1242356SN/A{ 1254873Sstever@eecs.umich.edu return "CPU Progress"; 1262356SN/A} 1272356SN/A 1288876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12910190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 13012680Sgiacomo.travaglini@arm.com _instMasterId(p->system->getMasterId(this, "inst")), 13112680Sgiacomo.travaglini@arm.com _dataMasterId(p->system->getMasterId(this, "data")), 13211050Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 1339814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1349220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 13510529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 13612284Sjose.marinho@arm.com previousCycle(0), previousState(CPU_STATE_SLEEP), 13710537Sandreas.hansson@arm.com functionTraceStream(nullptr), currentFunctionStart(0), 13810537Sandreas.hansson@arm.com currentFunctionEnd(0), functionEntryTick(0), 13911877Sbrandon.potter@amd.com addressMonitor(p->numThreads), 14012276Sanouk.vanlaer@arm.com syscallRetryLatency(p->syscallRetryLatency), 14112276Sanouk.vanlaer@arm.com pwrGatingLatency(p->pwr_gating_latency), 14212277Sjose.marinho@arm.com powerGatingOnIdle(p->power_gating_on_idle), 14312276Sanouk.vanlaer@arm.com enterPwrGatingEvent([this]{ enterPwrGating(); }, name()) 1442SN/A{ 1455712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1465712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1475712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1485712Shsul@eecs.umich.edu } 1495712Shsul@eecs.umich.edu 1502SN/A // add self to global list of CPUs 1512SN/A cpuList.push_back(this); 1522SN/A 15310190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 15410190Sakash.bagdia@arm.com _cpuId, _socketId); 1555712Shsul@eecs.umich.edu 1566221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1576221Snate@binkert.org maxThreadsPerCPU = numThreads; 1582SN/A 1592SN/A // allocate per-thread instruction-based event queues 1606221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1616221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1626221Snate@binkert.org comInstEventQueue[tid] = 1636221Snate@binkert.org new EventQueue("instruction-based event queue"); 1642SN/A 1652SN/A // 1662SN/A // set up instruction-count-based termination events, if any 1672SN/A // 1685606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1695606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1709749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1719749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1725606Snate@binkert.org } 1732SN/A 1749647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1759647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1769647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1779647Sdam.sunwoo@arm.com // exitting the simulation loop. 1789647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1799647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1809749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1819749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1829647Sdam.sunwoo@arm.com } 1839647Sdam.sunwoo@arm.com 1841400SN/A if (p->max_insts_all_threads != 0) { 1855606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1865606Snate@binkert.org 1872SN/A // allocate & initialize shared downcounter: each event will 1882SN/A // decrement this when triggered; simulation will terminate 1892SN/A // when counter reaches 0 1902SN/A int *counter = new int; 1916221Snate@binkert.org *counter = numThreads; 1926221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1935606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1946670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1955606Snate@binkert.org } 1962SN/A } 1972SN/A 198124SN/A // allocate per-thread load-based event queues 1996221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 2006221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 2016221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 202124SN/A 203124SN/A // 204124SN/A // set up instruction-count-based termination events, if any 205124SN/A // 2065606Snate@binkert.org if (p->max_loads_any_thread != 0) { 2075606Snate@binkert.org const char *cause = "a thread reached the max load count"; 2089749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 2099749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 2105606Snate@binkert.org } 211124SN/A 2121400SN/A if (p->max_loads_all_threads != 0) { 2135606Snate@binkert.org const char *cause = "all threads reached the max load count"; 214124SN/A // allocate & initialize shared downcounter: each event will 215124SN/A // decrement this when triggered; simulation will terminate 216124SN/A // when counter reaches 0 217124SN/A int *counter = new int; 2186221Snate@binkert.org *counter = numThreads; 2196221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2205606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2216221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2225606Snate@binkert.org } 223124SN/A } 224124SN/A 2251191SN/A functionTracingEnabled = false; 2265529Snate@binkert.org if (p->function_trace) { 2278634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 22811359Sandreas@sandberg.pp.se functionTraceStream = simout.findOrCreate(fname)->stream(); 2298634Schris.emmons@arm.com 2301191SN/A currentFunctionStart = currentFunctionEnd = 0; 2315529Snate@binkert.org functionEntryTick = p->function_trace_start; 2321191SN/A 2335529Snate@binkert.org if (p->function_trace_start == 0) { 2341191SN/A functionTracingEnabled = true; 2351191SN/A } else { 23612085Sspwilson2@wisc.edu Event *event = new EventFunctionWrapper( 23712085Sspwilson2@wisc.edu [this]{ enableFunctionTrace(); }, name(), true); 2385606Snate@binkert.org schedule(event, p->function_trace_start); 2391191SN/A } 2401191SN/A } 2418876Sandreas.hansson@arm.com 2428876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2438876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2449433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 24511221Sandreas.sandberg@arm.com fatal_if(interrupts.size() != numThreads, 24611221Sandreas.sandberg@arm.com "CPU %s has %i interrupt controllers, but is expecting one " 24711221Sandreas.sandberg@arm.com "per thread (%i)\n", 24811221Sandreas.sandberg@arm.com name(), interrupts.size(), numThreads); 24911221Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 25011221Sandreas.sandberg@arm.com interrupts[tid]->setCPU(this); 2518876Sandreas.hansson@arm.com } 2525810Sgblack@eecs.umich.edu 2538779Sgblack@eecs.umich.edu if (FullSystem) { 2548779Sgblack@eecs.umich.edu if (params()->profile) 25512127Sspwilson2@wisc.edu profileEvent = new EventFunctionWrapper( 25612127Sspwilson2@wisc.edu [this]{ processProfileEvent(); }, 25712127Sspwilson2@wisc.edu name()); 2588779Sgblack@eecs.umich.edu } 2595529Snate@binkert.org tracer = params()->tracer; 2609384SAndreas.Sandberg@arm.com 2619384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2629384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2639384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2649384SAndreas.Sandberg@arm.com } 2651917SN/A} 2661191SN/A 2671191SN/Avoid 2681191SN/ABaseCPU::enableFunctionTrace() 2691191SN/A{ 2701191SN/A functionTracingEnabled = true; 2711191SN/A} 2721191SN/A 2731191SN/ABaseCPU::~BaseCPU() 2741191SN/A{ 2759086Sandreas.hansson@arm.com delete profileEvent; 2769086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2779086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2781191SN/A} 2791191SN/A 2801129SN/Avoid 28111148Smitch.hayenga@arm.comBaseCPU::armMonitor(ThreadID tid, Addr address) 28210529Smorr@cs.wisc.edu{ 28311148Smitch.hayenga@arm.com assert(tid < numThreads); 28411148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 28511148Smitch.hayenga@arm.com 28611148Smitch.hayenga@arm.com monitor.armed = true; 28711148Smitch.hayenga@arm.com monitor.vAddr = address; 28811148Smitch.hayenga@arm.com monitor.pAddr = 0x0; 28911148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 29010529Smorr@cs.wisc.edu} 29110529Smorr@cs.wisc.edu 29210529Smorr@cs.wisc.edubool 29311148Smitch.hayenga@arm.comBaseCPU::mwait(ThreadID tid, PacketPtr pkt) 29410529Smorr@cs.wisc.edu{ 29511148Smitch.hayenga@arm.com assert(tid < numThreads); 29611148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 29711148Smitch.hayenga@arm.com 29811325Ssteve.reinhardt@amd.com if (!monitor.gotWakeup) { 29910529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 30010529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 30110529Smorr@cs.wisc.edu 30210529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 30311148Smitch.hayenga@arm.com monitor.pAddr = pkt->getAddr() & mask; 30411148Smitch.hayenga@arm.com monitor.waiting = true; 30510529Smorr@cs.wisc.edu 30611148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 30711148Smitch.hayenga@arm.com "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 30810529Smorr@cs.wisc.edu return true; 30910529Smorr@cs.wisc.edu } else { 31011148Smitch.hayenga@arm.com monitor.gotWakeup = false; 31110529Smorr@cs.wisc.edu return false; 31210529Smorr@cs.wisc.edu } 31310529Smorr@cs.wisc.edu} 31410529Smorr@cs.wisc.edu 31510529Smorr@cs.wisc.eduvoid 31612406Sgabeblack@google.comBaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) 31710529Smorr@cs.wisc.edu{ 31811148Smitch.hayenga@arm.com assert(tid < numThreads); 31911148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 32011148Smitch.hayenga@arm.com 32110529Smorr@cs.wisc.edu Request req; 32211148Smitch.hayenga@arm.com Addr addr = monitor.vAddr; 32310529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 32410529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 32510529Smorr@cs.wisc.edu int size = block_size; 32610529Smorr@cs.wisc.edu 32710529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 32810529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 32910529Smorr@cs.wisc.edu 33010529Smorr@cs.wisc.edu if (secondAddr > addr) 33110529Smorr@cs.wisc.edu size = secondAddr - addr; 33210529Smorr@cs.wisc.edu 33310529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 33410529Smorr@cs.wisc.edu 33510529Smorr@cs.wisc.edu // translate to physical address 33610529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 33710529Smorr@cs.wisc.edu assert(fault == NoFault); 33810529Smorr@cs.wisc.edu 33911148Smitch.hayenga@arm.com monitor.pAddr = req.getPaddr() & mask; 34011148Smitch.hayenga@arm.com monitor.waiting = true; 34110529Smorr@cs.wisc.edu 34211148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 34311148Smitch.hayenga@arm.com tid, monitor.vAddr, monitor.pAddr); 34410529Smorr@cs.wisc.edu} 34510529Smorr@cs.wisc.edu 34610529Smorr@cs.wisc.eduvoid 3471129SN/ABaseCPU::init() 3481129SN/A{ 3499523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3502680Sktlim@umich.edu registerThreadContexts(); 3519523SAndreas.Sandberg@ARM.com 3529523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3539523SAndreas.Sandberg@ARM.com } 3541129SN/A} 355180SN/A 3562SN/Avoid 3571917SN/ABaseCPU::startup() 3581917SN/A{ 3598779Sgblack@eecs.umich.edu if (FullSystem) { 3609433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3618779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3628779Sgblack@eecs.umich.edu } 3632356SN/A 3645529Snate@binkert.org if (params()->progress_interval) { 3659179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3662356SN/A } 36711526Sdavid.guillen@arm.com 36812276Sanouk.vanlaer@arm.com if (_switchedOut) 36912276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 37012276Sanouk.vanlaer@arm.com 37111526Sdavid.guillen@arm.com // Assumption CPU start to operate instantaneously without any latency 37211526Sdavid.guillen@arm.com if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED) 37311526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 37411526Sdavid.guillen@arm.com 3751917SN/A} 3761917SN/A 37710464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 37810464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 37910464SAndreas.Sandberg@ARM.com{ 38010464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 38110464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 38210464SAndreas.Sandberg@ARM.com 38310464SAndreas.Sandberg@ARM.com return ptr; 38410464SAndreas.Sandberg@ARM.com} 38510464SAndreas.Sandberg@ARM.com 38610464SAndreas.Sandberg@ARM.comvoid 38710464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 38810464SAndreas.Sandberg@ARM.com{ 38912284Sjose.marinho@arm.com ppAllCycles = pmuProbePoint("Cycles"); 39012284Sjose.marinho@arm.com ppActiveCycles = pmuProbePoint("ActiveCycles"); 39110464SAndreas.Sandberg@ARM.com 39210464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 39310464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 39410464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 39510464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 39612284Sjose.marinho@arm.com 39712284Sjose.marinho@arm.com ppSleeping = new ProbePointArg<bool>(this->getProbeManager(), 39812284Sjose.marinho@arm.com "Sleeping"); 39910464SAndreas.Sandberg@ARM.com} 40010464SAndreas.Sandberg@ARM.com 40110464SAndreas.Sandberg@ARM.comvoid 40210464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 40310464SAndreas.Sandberg@ARM.com{ 40410464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 40510464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 40610464SAndreas.Sandberg@ARM.com 40710464SAndreas.Sandberg@ARM.com 40810464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 40910464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 41010464SAndreas.Sandberg@ARM.com 41110464SAndreas.Sandberg@ARM.com if (inst->isStore()) 41210643Snikos.nikoleris@gmail.com ppRetiredStores->notify(1); 41310464SAndreas.Sandberg@ARM.com 41410464SAndreas.Sandberg@ARM.com if (inst->isControl()) 41510464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 41610464SAndreas.Sandberg@ARM.com} 4171917SN/A 4181917SN/Avoid 4192SN/ABaseCPU::regStats() 4202SN/A{ 42111522Sstephan.diestelhorst@arm.com MemObject::regStats(); 42211522Sstephan.diestelhorst@arm.com 423729SN/A using namespace Stats; 424707SN/A 425707SN/A numCycles 426707SN/A .name(name() + ".numCycles") 427707SN/A .desc("number of cpu cycles simulated") 428707SN/A ; 429707SN/A 4307914SBrad.Beckmann@amd.com numWorkItemsStarted 4317914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 4327914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 4337914SBrad.Beckmann@amd.com ; 4347914SBrad.Beckmann@amd.com 4357914SBrad.Beckmann@amd.com numWorkItemsCompleted 4367914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4377914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4387914SBrad.Beckmann@amd.com ; 4397914SBrad.Beckmann@amd.com 4402680Sktlim@umich.edu int size = threadContexts.size(); 4412SN/A if (size > 1) { 4422SN/A for (int i = 0; i < size; ++i) { 4432SN/A stringstream namestr; 4442SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4452680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4462SN/A } 4472SN/A } else if (size == 1) 4482680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4492SN/A} 4502SN/A 4519294Sandreas.hansson@arm.comBaseMasterPort & 4529294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4538850Sandreas.hansson@arm.com{ 4548850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4558850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4568850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4579608Sandreas.hansson@arm.com // return a MasterPort pointer. 4588850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4598922Swilliam.wang@arm.com return getDataPort(); 4608850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4618922Swilliam.wang@arm.com return getInstPort(); 4628850Sandreas.hansson@arm.com else 4638922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4648850Sandreas.hansson@arm.com} 4658850Sandreas.hansson@arm.com 466180SN/Avoid 4672680Sktlim@umich.eduBaseCPU::registerThreadContexts() 468180SN/A{ 46911146Smitch.hayenga@arm.com assert(system->multiThread || numThreads == 1); 47011146Smitch.hayenga@arm.com 4716221Snate@binkert.org ThreadID size = threadContexts.size(); 4726221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4736221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4742378SN/A 47511146Smitch.hayenga@arm.com if (system->multiThread) { 47611146Smitch.hayenga@arm.com tc->setContextId(system->registerThreadContext(tc)); 47711146Smitch.hayenga@arm.com } else { 4785718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 47911146Smitch.hayenga@arm.com } 4808779Sgblack@eecs.umich.edu 4818779Sgblack@eecs.umich.edu if (!FullSystem) 4828779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 483180SN/A } 484180SN/A} 485180SN/A 48612276Sanouk.vanlaer@arm.comvoid 48712276Sanouk.vanlaer@arm.comBaseCPU::deschedulePowerGatingEvent() 48812276Sanouk.vanlaer@arm.com{ 48912276Sanouk.vanlaer@arm.com if (enterPwrGatingEvent.scheduled()){ 49012276Sanouk.vanlaer@arm.com deschedule(enterPwrGatingEvent); 49112276Sanouk.vanlaer@arm.com } 49212276Sanouk.vanlaer@arm.com} 49312276Sanouk.vanlaer@arm.com 49412276Sanouk.vanlaer@arm.comvoid 49512276Sanouk.vanlaer@arm.comBaseCPU::schedulePowerGatingEvent() 49612276Sanouk.vanlaer@arm.com{ 49712276Sanouk.vanlaer@arm.com for (auto tc : threadContexts) { 49812276Sanouk.vanlaer@arm.com if (tc->status() == ThreadContext::Active) 49912276Sanouk.vanlaer@arm.com return; 50012276Sanouk.vanlaer@arm.com } 50112276Sanouk.vanlaer@arm.com 50212277Sjose.marinho@arm.com if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED && 50312277Sjose.marinho@arm.com powerGatingOnIdle) { 50412276Sanouk.vanlaer@arm.com assert(!enterPwrGatingEvent.scheduled()); 50512276Sanouk.vanlaer@arm.com // Schedule a power gating event when clock gated for the specified 50612276Sanouk.vanlaer@arm.com // amount of time 50712276Sanouk.vanlaer@arm.com schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 50812276Sanouk.vanlaer@arm.com } 50912276Sanouk.vanlaer@arm.com} 510180SN/A 5114000Ssaidi@eecs.umich.eduint 5124000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 5134000Ssaidi@eecs.umich.edu{ 5146221Snate@binkert.org ThreadID size = threadContexts.size(); 5156221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 5166221Snate@binkert.org if (tc == threadContexts[tid]) 5176221Snate@binkert.org return tid; 5184000Ssaidi@eecs.umich.edu } 5194000Ssaidi@eecs.umich.edu return 0; 5204000Ssaidi@eecs.umich.edu} 5214000Ssaidi@eecs.umich.edu 522180SN/Avoid 52311526Sdavid.guillen@arm.comBaseCPU::activateContext(ThreadID thread_num) 52411526Sdavid.guillen@arm.com{ 52512276Sanouk.vanlaer@arm.com // Squash enter power gating event while cpu gets activated 52612276Sanouk.vanlaer@arm.com if (enterPwrGatingEvent.scheduled()) 52712276Sanouk.vanlaer@arm.com deschedule(enterPwrGatingEvent); 52811526Sdavid.guillen@arm.com // For any active thread running, update CPU power state to active (ON) 52911526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 53012284Sjose.marinho@arm.com 53112284Sjose.marinho@arm.com updateCycleCounters(CPU_STATE_WAKEUP); 53211526Sdavid.guillen@arm.com} 53311526Sdavid.guillen@arm.com 53411526Sdavid.guillen@arm.comvoid 53511526Sdavid.guillen@arm.comBaseCPU::suspendContext(ThreadID thread_num) 53611526Sdavid.guillen@arm.com{ 53711526Sdavid.guillen@arm.com // Check if all threads are suspended 53811526Sdavid.guillen@arm.com for (auto t : threadContexts) { 53911526Sdavid.guillen@arm.com if (t->status() != ThreadContext::Suspended) { 54011526Sdavid.guillen@arm.com return; 54111526Sdavid.guillen@arm.com } 54211526Sdavid.guillen@arm.com } 54311526Sdavid.guillen@arm.com 54412284Sjose.marinho@arm.com // All CPU thread are suspended, update cycle count 54512284Sjose.marinho@arm.com updateCycleCounters(CPU_STATE_SLEEP); 54612284Sjose.marinho@arm.com 54711526Sdavid.guillen@arm.com // All CPU threads suspended, enter lower power state for the CPU 54811526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::CLK_GATED); 54912276Sanouk.vanlaer@arm.com 55012277Sjose.marinho@arm.com // If pwrGatingLatency is set to 0 then this mechanism is disabled 55112277Sjose.marinho@arm.com if (powerGatingOnIdle) { 55212277Sjose.marinho@arm.com // Schedule power gating event when clock gated for pwrGatingLatency 55312277Sjose.marinho@arm.com // cycles 55412277Sjose.marinho@arm.com schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 55512277Sjose.marinho@arm.com } 55612276Sanouk.vanlaer@arm.com} 55712276Sanouk.vanlaer@arm.com 55812276Sanouk.vanlaer@arm.comvoid 55912284Sjose.marinho@arm.comBaseCPU::haltContext(ThreadID thread_num) 56012284Sjose.marinho@arm.com{ 56112284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_SLEEP); 56212284Sjose.marinho@arm.com} 56312284Sjose.marinho@arm.com 56412284Sjose.marinho@arm.comvoid 56512276Sanouk.vanlaer@arm.comBaseCPU::enterPwrGating(void) 56612276Sanouk.vanlaer@arm.com{ 56712276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 56811526Sdavid.guillen@arm.com} 56911526Sdavid.guillen@arm.com 57011526Sdavid.guillen@arm.comvoid 5712798Sktlim@umich.eduBaseCPU::switchOut() 572180SN/A{ 5739430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 5749430SAndreas.Sandberg@ARM.com _switchedOut = true; 5752359SN/A if (profileEvent && profileEvent->scheduled()) 5765606Snate@binkert.org deschedule(profileEvent); 5779446SAndreas.Sandberg@ARM.com 5789446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 5799446SAndreas.Sandberg@ARM.com // it gets switched in later. 5809446SAndreas.Sandberg@ARM.com flushTLBs(); 58112276Sanouk.vanlaer@arm.com 58212276Sanouk.vanlaer@arm.com // Go to the power gating state 58312276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 584180SN/A} 585180SN/A 586180SN/Avoid 5878737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 588180SN/A{ 5892680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 5909152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 5919430SAndreas.Sandberg@ARM.com assert(_switchedOut); 5929430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 5939332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 5949332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 59512276Sanouk.vanlaer@arm.com // Take over the power state of the switchedOut CPU 59612276Sanouk.vanlaer@arm.com ClockedObject::pwrState(oldCPU->pwrState()); 59712284Sjose.marinho@arm.com 59812284Sjose.marinho@arm.com previousState = oldCPU->previousState; 59912284Sjose.marinho@arm.com previousCycle = oldCPU->previousCycle; 60012284Sjose.marinho@arm.com 6019430SAndreas.Sandberg@ARM.com _switchedOut = false; 6025712Shsul@eecs.umich.edu 6036221Snate@binkert.org ThreadID size = threadContexts.size(); 6046221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 6052680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 6062680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 607180SN/A 6082680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 6092651Ssaidi@eecs.umich.edu 6102680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 6112651Ssaidi@eecs.umich.edu 6125714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 6135715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 6145714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 6152359SN/A 6165875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 6175875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 6185875Ssteve.reinhardt@amd.com * point. 6195875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 6205217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 6215875Ssteve.reinhardt@amd.com */ 6227781SAli.Saidi@ARM.com 6239294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 6249294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 6259294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 6269294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 6277781SAli.Saidi@ARM.com 6287781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 6299178Sandreas.hansson@arm.com if (new_itb_port) { 6309178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 6317781SAli.Saidi@ARM.com assert(old_itb_port); 6329178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 6339294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 6349178Sandreas.hansson@arm.com old_itb_port->unbind(); 6358922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 6367781SAli.Saidi@ARM.com } 6379178Sandreas.hansson@arm.com if (new_dtb_port) { 6389178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 6397781SAli.Saidi@ARM.com assert(old_dtb_port); 6409178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 6419294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 6429178Sandreas.hansson@arm.com old_dtb_port->unbind(); 6438922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 6447781SAli.Saidi@ARM.com } 64510194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 64610194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 6478733Sgeoffrey.blake@arm.com 6488887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 6498887Sgeoffrey.blake@arm.com // objects over in the switch 6508887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 6518887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 6528887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 6539294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 6548922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 6559294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 6568922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 6579294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 6588922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 6599294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 6608922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 6618733Sgeoffrey.blake@arm.com 66210194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 66310194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 66410194SGeoffrey.Blake@arm.com 6658887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 6669178Sandreas.hansson@arm.com if (new_checker_itb_port) { 6679178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 6688887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 6699178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 6709294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6719294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 6729178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 6738922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 6748887Sgeoffrey.blake@arm.com } 6759178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 6769178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 6778887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 6789178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 6799294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6809294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 6819178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 6828922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 6838887Sgeoffrey.blake@arm.com } 6848733Sgeoffrey.blake@arm.com } 685180SN/A } 686605SN/A 6873520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 68811150Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 68911150Smitch.hayenga@arm.com interrupts[tid]->setCPU(this); 69011150Smitch.hayenga@arm.com } 69111150Smitch.hayenga@arm.com oldCPU->interrupts.clear(); 6922254SN/A 6938779Sgblack@eecs.umich.edu if (FullSystem) { 6948779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 6958779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 6962254SN/A 6978779Sgblack@eecs.umich.edu if (profileEvent) 6988779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 6998779Sgblack@eecs.umich.edu } 7004192Sktlim@umich.edu 7019178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 7029178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 7039178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 7049178Sandreas.hansson@arm.com // we are switching to. 7059178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 7069178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 7079294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 7089178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 7099178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 7104192Sktlim@umich.edu 7119178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 7129178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 7139294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 7149178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 7159178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 716180SN/A} 717180SN/A 7189446SAndreas.Sandberg@ARM.comvoid 7199446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 7209446SAndreas.Sandberg@ARM.com{ 7219446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 7229446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 7239446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 7249446SAndreas.Sandberg@ARM.com 7259446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 7269446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 7279446SAndreas.Sandberg@ARM.com if (checker) { 7289446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 7299446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 7309446SAndreas.Sandberg@ARM.com } 7319446SAndreas.Sandberg@ARM.com } 7329446SAndreas.Sandberg@ARM.com} 7339446SAndreas.Sandberg@ARM.com 73412127Sspwilson2@wisc.eduvoid 73512127Sspwilson2@wisc.eduBaseCPU::processProfileEvent() 73612127Sspwilson2@wisc.edu{ 73712127Sspwilson2@wisc.edu ThreadID size = threadContexts.size(); 738180SN/A 73912127Sspwilson2@wisc.edu for (ThreadID i = 0; i < size; ++i) 74012127Sspwilson2@wisc.edu threadContexts[i]->profileSample(); 7411917SN/A 74212127Sspwilson2@wisc.edu schedule(profileEvent, curTick() + params()->profile); 7431917SN/A} 7441917SN/A 7452SN/Avoid 74610905Sandreas.sandberg@arm.comBaseCPU::serialize(CheckpointOut &cp) const 747921SN/A{ 7484000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 7499332Sdam.sunwoo@arm.com 7509448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7519448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 7529448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 7539448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 7549448SAndreas.Sandberg@ARM.com * system. */ 7559448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 7569332Sdam.sunwoo@arm.com 7579448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 7589448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 75910905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 76011150Smitch.hayenga@arm.com interrupts[i]->serialize(cp); 76110905Sandreas.sandberg@arm.com serializeThread(cp, i); 7629448SAndreas.Sandberg@ARM.com } 7639448SAndreas.Sandberg@ARM.com } 764921SN/A} 765921SN/A 766921SN/Avoid 76710905Sandreas.sandberg@arm.comBaseCPU::unserialize(CheckpointIn &cp) 768921SN/A{ 7694000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 7709448SAndreas.Sandberg@ARM.com 7719448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7729448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 7739448SAndreas.Sandberg@ARM.com 7749448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 77510905Sandreas.sandberg@arm.com for (ThreadID i = 0; i < numThreads; ++i) { 77610905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 77711150Smitch.hayenga@arm.com interrupts[i]->unserialize(cp); 77810905Sandreas.sandberg@arm.com unserializeThread(cp, i); 77910905Sandreas.sandberg@arm.com } 7809448SAndreas.Sandberg@ARM.com } 781921SN/A} 782921SN/A 7831191SN/Avoid 7849749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 7859749Sandreas@sandberg.pp.se{ 7869749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 7879983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7889749Sandreas@sandberg.pp.se 7899749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 7909749Sandreas@sandberg.pp.se} 7919749Sandreas@sandberg.pp.se 79211415SGeoffrey.Blake@arm.comuint64_t 79311415SGeoffrey.Blake@arm.comBaseCPU::getCurrentInstCount(ThreadID tid) 79411415SGeoffrey.Blake@arm.com{ 79511415SGeoffrey.Blake@arm.com return Tick(comInstEventQueue[tid]->getCurTick()); 79611415SGeoffrey.Blake@arm.com} 79711415SGeoffrey.Blake@arm.com 79810529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 79910529Smorr@cs.wisc.edu armed = false; 80010529Smorr@cs.wisc.edu waiting = false; 80110529Smorr@cs.wisc.edu gotWakeup = false; 80210529Smorr@cs.wisc.edu} 80310529Smorr@cs.wisc.edu 80410529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 80510529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 80611321Ssteve.reinhardt@amd.com if (armed && waiting) { 80711321Ssteve.reinhardt@amd.com if (pAddr == pkt->getAddr()) { 80810529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 80910529Smorr@cs.wisc.edu pkt->getAddr()); 81010529Smorr@cs.wisc.edu waiting = false; 81110529Smorr@cs.wisc.edu return true; 81210529Smorr@cs.wisc.edu } 81310529Smorr@cs.wisc.edu } 81410529Smorr@cs.wisc.edu return false; 81510529Smorr@cs.wisc.edu} 81610529Smorr@cs.wisc.edu 8179749Sandreas@sandberg.pp.sevoid 8189749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 8199749Sandreas@sandberg.pp.se{ 8209749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 8219983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 8229749Sandreas@sandberg.pp.se 8239749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 8249749Sandreas@sandberg.pp.se} 8259749Sandreas@sandberg.pp.se 8269749Sandreas@sandberg.pp.se 8279749Sandreas@sandberg.pp.sevoid 8281191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 8291191SN/A{ 8301191SN/A if (!debugSymbolTable) 8311191SN/A return; 8321191SN/A 8331191SN/A // if pc enters different function, print new function symbol and 8341191SN/A // update saved range. Otherwise do nothing. 8351191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 8361191SN/A string sym_str; 8371191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 8381191SN/A currentFunctionStart, 8391191SN/A currentFunctionEnd); 8401191SN/A 8411191SN/A if (!found) { 8421191SN/A // no symbol found: use addr as label 8431191SN/A sym_str = csprintf("0x%x", pc); 8441191SN/A currentFunctionStart = pc; 8451191SN/A currentFunctionEnd = pc + 1; 8461191SN/A } 8471191SN/A 8481191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 8497823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 8507823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 8511191SN/A } 8521191SN/A} 85312122Sjose.marinho@arm.com 85412122Sjose.marinho@arm.combool 85512122Sjose.marinho@arm.comBaseCPU::waitForRemoteGDB() const 85612122Sjose.marinho@arm.com{ 85712122Sjose.marinho@arm.com return params()->wait_for_remote_gdb; 85812122Sjose.marinho@arm.com} 859