base.cc revision 12127
12SN/A/* 211526Sdavid.guillen@arm.com * Copyright (c) 2011-2012,2016 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 4811793Sbrandon.potter@amd.com#include "cpu/base.hh" 4911793Sbrandon.potter@amd.com 501388SN/A#include <iostream> 518229Snate@binkert.org#include <sstream> 522SN/A#include <string> 532SN/A 547781SAli.Saidi@ARM.com#include "arch/tlb.hh" 5511793Sbrandon.potter@amd.com#include "base/cprintf.hh" 568229Snate@binkert.org#include "base/loader/symtab.hh" 571191SN/A#include "base/misc.hh" 581388SN/A#include "base/output.hh" 595529Snate@binkert.org#include "base/trace.hh" 6010529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 612651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 628229Snate@binkert.org#include "cpu/profile.hh" 632680Sktlim@umich.edu#include "cpu/thread_context.hh" 6410529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 658232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6610529Smorr@cs.wisc.edu#include "mem/page_table.hh" 675529Snate@binkert.org#include "params/BaseCPU.hh" 6811526Sdavid.guillen@arm.com#include "sim/clocked_object.hh" 698779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 702190SN/A#include "sim/process.hh" 7156SN/A#include "sim/sim_events.hh" 728229Snate@binkert.org#include "sim/sim_exit.hh" 732190SN/A#include "sim/system.hh" 742SN/A 752359SN/A// Hack 762359SN/A#include "sim/stat_control.hh" 772359SN/A 782SN/Ausing namespace std; 792SN/A 802SN/Avector<BaseCPU *> BaseCPU::cpuList; 812SN/A 822SN/A// This variable reflects the max number of threads in any CPU. Be 832SN/A// careful to only use it once all the CPUs that you care about have 842SN/A// been initialized 852SN/Aint maxThreadsPerCPU = 1; 862SN/A 875606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 886144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 896144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 903126Sktlim@umich.edu{ 916144Sksewell@umich.edu if (_interval) 927823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 933126Sktlim@umich.edu} 943126Sktlim@umich.edu 952356SN/Avoid 962356SN/ACPUProgressEvent::process() 972356SN/A{ 988834Satgutier@umich.edu Counter temp = cpu->totalOps(); 9910786Smalek.musleh@gmail.com 10010786Smalek.musleh@gmail.com if (_repeatEvent) 10110786Smalek.musleh@gmail.com cpu->schedule(this, curTick() + _interval); 10210786Smalek.musleh@gmail.com 10311321Ssteve.reinhardt@amd.com if (cpu->switchedOut()) { 10410786Smalek.musleh@gmail.com return; 10510786Smalek.musleh@gmail.com } 10610786Smalek.musleh@gmail.com 1072356SN/A#ifndef NDEBUG 1089179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 1092367SN/A 1106144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1116144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1126144Sksewell@umich.edu ipc); 1132356SN/A ipc = 0.0; 1142367SN/A#else 1156144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1167823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1176144Sksewell@umich.edu temp - lastNumInst); 1182367SN/A#endif 1192356SN/A lastNumInst = temp; 1202356SN/A} 1212356SN/A 1222356SN/Aconst char * 1235336Shines@cs.fsu.eduCPUProgressEvent::description() const 1242356SN/A{ 1254873Sstever@eecs.umich.edu return "CPU Progress"; 1262356SN/A} 1272356SN/A 1288876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12910190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1308832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1318832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 13211050Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 1339814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1349220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 13510529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 13610537Sandreas.hansson@arm.com functionTraceStream(nullptr), currentFunctionStart(0), 13710537Sandreas.hansson@arm.com currentFunctionEnd(0), functionEntryTick(0), 13811877Sbrandon.potter@amd.com addressMonitor(p->numThreads), 13911877Sbrandon.potter@amd.com syscallRetryLatency(p->syscallRetryLatency) 1402SN/A{ 1415712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1425712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1435712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1445712Shsul@eecs.umich.edu } 1455712Shsul@eecs.umich.edu 1462SN/A // add self to global list of CPUs 1472SN/A cpuList.push_back(this); 1482SN/A 14910190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 15010190Sakash.bagdia@arm.com _cpuId, _socketId); 1515712Shsul@eecs.umich.edu 1526221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1536221Snate@binkert.org maxThreadsPerCPU = numThreads; 1542SN/A 1552SN/A // allocate per-thread instruction-based event queues 1566221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1576221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1586221Snate@binkert.org comInstEventQueue[tid] = 1596221Snate@binkert.org new EventQueue("instruction-based event queue"); 1602SN/A 1612SN/A // 1622SN/A // set up instruction-count-based termination events, if any 1632SN/A // 1645606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1655606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1669749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1679749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1685606Snate@binkert.org } 1692SN/A 1709647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1719647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1729647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1739647Sdam.sunwoo@arm.com // exitting the simulation loop. 1749647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1759647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1769749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1779749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1789647Sdam.sunwoo@arm.com } 1799647Sdam.sunwoo@arm.com 1801400SN/A if (p->max_insts_all_threads != 0) { 1815606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1825606Snate@binkert.org 1832SN/A // allocate & initialize shared downcounter: each event will 1842SN/A // decrement this when triggered; simulation will terminate 1852SN/A // when counter reaches 0 1862SN/A int *counter = new int; 1876221Snate@binkert.org *counter = numThreads; 1886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1895606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1906670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1915606Snate@binkert.org } 1922SN/A } 1932SN/A 194124SN/A // allocate per-thread load-based event queues 1956221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1976221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 198124SN/A 199124SN/A // 200124SN/A // set up instruction-count-based termination events, if any 201124SN/A // 2025606Snate@binkert.org if (p->max_loads_any_thread != 0) { 2035606Snate@binkert.org const char *cause = "a thread reached the max load count"; 2049749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 2059749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 2065606Snate@binkert.org } 207124SN/A 2081400SN/A if (p->max_loads_all_threads != 0) { 2095606Snate@binkert.org const char *cause = "all threads reached the max load count"; 210124SN/A // allocate & initialize shared downcounter: each event will 211124SN/A // decrement this when triggered; simulation will terminate 212124SN/A // when counter reaches 0 213124SN/A int *counter = new int; 2146221Snate@binkert.org *counter = numThreads; 2156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2165606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2176221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2185606Snate@binkert.org } 219124SN/A } 220124SN/A 2211191SN/A functionTracingEnabled = false; 2225529Snate@binkert.org if (p->function_trace) { 2238634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 22411359Sandreas@sandberg.pp.se functionTraceStream = simout.findOrCreate(fname)->stream(); 2258634Schris.emmons@arm.com 2261191SN/A currentFunctionStart = currentFunctionEnd = 0; 2275529Snate@binkert.org functionEntryTick = p->function_trace_start; 2281191SN/A 2295529Snate@binkert.org if (p->function_trace_start == 0) { 2301191SN/A functionTracingEnabled = true; 2311191SN/A } else { 23212085Sspwilson2@wisc.edu Event *event = new EventFunctionWrapper( 23312085Sspwilson2@wisc.edu [this]{ enableFunctionTrace(); }, name(), true); 2345606Snate@binkert.org schedule(event, p->function_trace_start); 2351191SN/A } 2361191SN/A } 2378876Sandreas.hansson@arm.com 2388876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2398876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2409433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 24111221Sandreas.sandberg@arm.com fatal_if(interrupts.size() != numThreads, 24211221Sandreas.sandberg@arm.com "CPU %s has %i interrupt controllers, but is expecting one " 24311221Sandreas.sandberg@arm.com "per thread (%i)\n", 24411221Sandreas.sandberg@arm.com name(), interrupts.size(), numThreads); 24511221Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 24611221Sandreas.sandberg@arm.com interrupts[tid]->setCPU(this); 2478876Sandreas.hansson@arm.com } 2485810Sgblack@eecs.umich.edu 2498779Sgblack@eecs.umich.edu if (FullSystem) { 2508779Sgblack@eecs.umich.edu if (params()->profile) 25112127Sspwilson2@wisc.edu profileEvent = new EventFunctionWrapper( 25212127Sspwilson2@wisc.edu [this]{ processProfileEvent(); }, 25312127Sspwilson2@wisc.edu name()); 2548779Sgblack@eecs.umich.edu } 2555529Snate@binkert.org tracer = params()->tracer; 2569384SAndreas.Sandberg@arm.com 2579384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2589384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2599384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2609384SAndreas.Sandberg@arm.com } 2611917SN/A} 2621191SN/A 2631191SN/Avoid 2641191SN/ABaseCPU::enableFunctionTrace() 2651191SN/A{ 2661191SN/A functionTracingEnabled = true; 2671191SN/A} 2681191SN/A 2691191SN/ABaseCPU::~BaseCPU() 2701191SN/A{ 2719086Sandreas.hansson@arm.com delete profileEvent; 2729086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2739086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2741191SN/A} 2751191SN/A 2761129SN/Avoid 27711148Smitch.hayenga@arm.comBaseCPU::armMonitor(ThreadID tid, Addr address) 27810529Smorr@cs.wisc.edu{ 27911148Smitch.hayenga@arm.com assert(tid < numThreads); 28011148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 28111148Smitch.hayenga@arm.com 28211148Smitch.hayenga@arm.com monitor.armed = true; 28311148Smitch.hayenga@arm.com monitor.vAddr = address; 28411148Smitch.hayenga@arm.com monitor.pAddr = 0x0; 28511148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 28610529Smorr@cs.wisc.edu} 28710529Smorr@cs.wisc.edu 28810529Smorr@cs.wisc.edubool 28911148Smitch.hayenga@arm.comBaseCPU::mwait(ThreadID tid, PacketPtr pkt) 29010529Smorr@cs.wisc.edu{ 29111148Smitch.hayenga@arm.com assert(tid < numThreads); 29211148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 29311148Smitch.hayenga@arm.com 29411325Ssteve.reinhardt@amd.com if (!monitor.gotWakeup) { 29510529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 29610529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 29710529Smorr@cs.wisc.edu 29810529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 29911148Smitch.hayenga@arm.com monitor.pAddr = pkt->getAddr() & mask; 30011148Smitch.hayenga@arm.com monitor.waiting = true; 30110529Smorr@cs.wisc.edu 30211148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 30311148Smitch.hayenga@arm.com "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 30410529Smorr@cs.wisc.edu return true; 30510529Smorr@cs.wisc.edu } else { 30611148Smitch.hayenga@arm.com monitor.gotWakeup = false; 30710529Smorr@cs.wisc.edu return false; 30810529Smorr@cs.wisc.edu } 30910529Smorr@cs.wisc.edu} 31010529Smorr@cs.wisc.edu 31110529Smorr@cs.wisc.eduvoid 31211148Smitch.hayenga@arm.comBaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb) 31310529Smorr@cs.wisc.edu{ 31411148Smitch.hayenga@arm.com assert(tid < numThreads); 31511148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 31611148Smitch.hayenga@arm.com 31710529Smorr@cs.wisc.edu Request req; 31811148Smitch.hayenga@arm.com Addr addr = monitor.vAddr; 31910529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 32010529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 32110529Smorr@cs.wisc.edu int size = block_size; 32210529Smorr@cs.wisc.edu 32310529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 32410529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 32510529Smorr@cs.wisc.edu 32610529Smorr@cs.wisc.edu if (secondAddr > addr) 32710529Smorr@cs.wisc.edu size = secondAddr - addr; 32810529Smorr@cs.wisc.edu 32910529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 33010529Smorr@cs.wisc.edu 33110529Smorr@cs.wisc.edu // translate to physical address 33210529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 33310529Smorr@cs.wisc.edu assert(fault == NoFault); 33410529Smorr@cs.wisc.edu 33511148Smitch.hayenga@arm.com monitor.pAddr = req.getPaddr() & mask; 33611148Smitch.hayenga@arm.com monitor.waiting = true; 33710529Smorr@cs.wisc.edu 33811148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 33911148Smitch.hayenga@arm.com tid, monitor.vAddr, monitor.pAddr); 34010529Smorr@cs.wisc.edu} 34110529Smorr@cs.wisc.edu 34210529Smorr@cs.wisc.eduvoid 3431129SN/ABaseCPU::init() 3441129SN/A{ 3459523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3462680Sktlim@umich.edu registerThreadContexts(); 3479523SAndreas.Sandberg@ARM.com 3489523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3499523SAndreas.Sandberg@ARM.com } 3501129SN/A} 351180SN/A 3522SN/Avoid 3531917SN/ABaseCPU::startup() 3541917SN/A{ 3558779Sgblack@eecs.umich.edu if (FullSystem) { 3569433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3578779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3588779Sgblack@eecs.umich.edu } 3592356SN/A 3605529Snate@binkert.org if (params()->progress_interval) { 3619179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3622356SN/A } 36311526Sdavid.guillen@arm.com 36411526Sdavid.guillen@arm.com // Assumption CPU start to operate instantaneously without any latency 36511526Sdavid.guillen@arm.com if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED) 36611526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 36711526Sdavid.guillen@arm.com 3681917SN/A} 3691917SN/A 37010464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 37110464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 37210464SAndreas.Sandberg@ARM.com{ 37310464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 37410464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 37510464SAndreas.Sandberg@ARM.com 37610464SAndreas.Sandberg@ARM.com return ptr; 37710464SAndreas.Sandberg@ARM.com} 37810464SAndreas.Sandberg@ARM.com 37910464SAndreas.Sandberg@ARM.comvoid 38010464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 38110464SAndreas.Sandberg@ARM.com{ 38210464SAndreas.Sandberg@ARM.com ppCycles = pmuProbePoint("Cycles"); 38310464SAndreas.Sandberg@ARM.com 38410464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 38510464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 38610464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 38710464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 38810464SAndreas.Sandberg@ARM.com} 38910464SAndreas.Sandberg@ARM.com 39010464SAndreas.Sandberg@ARM.comvoid 39110464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 39210464SAndreas.Sandberg@ARM.com{ 39310464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 39410464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 39510464SAndreas.Sandberg@ARM.com 39610464SAndreas.Sandberg@ARM.com 39710464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 39810464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 39910464SAndreas.Sandberg@ARM.com 40010464SAndreas.Sandberg@ARM.com if (inst->isStore()) 40110643Snikos.nikoleris@gmail.com ppRetiredStores->notify(1); 40210464SAndreas.Sandberg@ARM.com 40310464SAndreas.Sandberg@ARM.com if (inst->isControl()) 40410464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 40510464SAndreas.Sandberg@ARM.com} 4061917SN/A 4071917SN/Avoid 4082SN/ABaseCPU::regStats() 4092SN/A{ 41011522Sstephan.diestelhorst@arm.com MemObject::regStats(); 41111522Sstephan.diestelhorst@arm.com 412729SN/A using namespace Stats; 413707SN/A 414707SN/A numCycles 415707SN/A .name(name() + ".numCycles") 416707SN/A .desc("number of cpu cycles simulated") 417707SN/A ; 418707SN/A 4197914SBrad.Beckmann@amd.com numWorkItemsStarted 4207914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 4217914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 4227914SBrad.Beckmann@amd.com ; 4237914SBrad.Beckmann@amd.com 4247914SBrad.Beckmann@amd.com numWorkItemsCompleted 4257914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4267914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4277914SBrad.Beckmann@amd.com ; 4287914SBrad.Beckmann@amd.com 4292680Sktlim@umich.edu int size = threadContexts.size(); 4302SN/A if (size > 1) { 4312SN/A for (int i = 0; i < size; ++i) { 4322SN/A stringstream namestr; 4332SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4342680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4352SN/A } 4362SN/A } else if (size == 1) 4372680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4382SN/A} 4392SN/A 4409294Sandreas.hansson@arm.comBaseMasterPort & 4419294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4428850Sandreas.hansson@arm.com{ 4438850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4448850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4458850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4469608Sandreas.hansson@arm.com // return a MasterPort pointer. 4478850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4488922Swilliam.wang@arm.com return getDataPort(); 4498850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4508922Swilliam.wang@arm.com return getInstPort(); 4518850Sandreas.hansson@arm.com else 4528922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4538850Sandreas.hansson@arm.com} 4548850Sandreas.hansson@arm.com 455180SN/Avoid 4562680Sktlim@umich.eduBaseCPU::registerThreadContexts() 457180SN/A{ 45811146Smitch.hayenga@arm.com assert(system->multiThread || numThreads == 1); 45911146Smitch.hayenga@arm.com 4606221Snate@binkert.org ThreadID size = threadContexts.size(); 4616221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4626221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4632378SN/A 46411146Smitch.hayenga@arm.com if (system->multiThread) { 46511146Smitch.hayenga@arm.com tc->setContextId(system->registerThreadContext(tc)); 46611146Smitch.hayenga@arm.com } else { 4675718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 46811146Smitch.hayenga@arm.com } 4698779Sgblack@eecs.umich.edu 4708779Sgblack@eecs.umich.edu if (!FullSystem) 4718779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 472180SN/A } 473180SN/A} 474180SN/A 475180SN/A 4764000Ssaidi@eecs.umich.eduint 4774000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 4784000Ssaidi@eecs.umich.edu{ 4796221Snate@binkert.org ThreadID size = threadContexts.size(); 4806221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4816221Snate@binkert.org if (tc == threadContexts[tid]) 4826221Snate@binkert.org return tid; 4834000Ssaidi@eecs.umich.edu } 4844000Ssaidi@eecs.umich.edu return 0; 4854000Ssaidi@eecs.umich.edu} 4864000Ssaidi@eecs.umich.edu 487180SN/Avoid 48811526Sdavid.guillen@arm.comBaseCPU::activateContext(ThreadID thread_num) 48911526Sdavid.guillen@arm.com{ 49011526Sdavid.guillen@arm.com // For any active thread running, update CPU power state to active (ON) 49111526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 49211526Sdavid.guillen@arm.com} 49311526Sdavid.guillen@arm.com 49411526Sdavid.guillen@arm.comvoid 49511526Sdavid.guillen@arm.comBaseCPU::suspendContext(ThreadID thread_num) 49611526Sdavid.guillen@arm.com{ 49711526Sdavid.guillen@arm.com // Check if all threads are suspended 49811526Sdavid.guillen@arm.com for (auto t : threadContexts) { 49911526Sdavid.guillen@arm.com if (t->status() != ThreadContext::Suspended) { 50011526Sdavid.guillen@arm.com return; 50111526Sdavid.guillen@arm.com } 50211526Sdavid.guillen@arm.com } 50311526Sdavid.guillen@arm.com 50411526Sdavid.guillen@arm.com // All CPU threads suspended, enter lower power state for the CPU 50511526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::CLK_GATED); 50611526Sdavid.guillen@arm.com} 50711526Sdavid.guillen@arm.com 50811526Sdavid.guillen@arm.comvoid 5092798Sktlim@umich.eduBaseCPU::switchOut() 510180SN/A{ 5119430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 5129430SAndreas.Sandberg@ARM.com _switchedOut = true; 5132359SN/A if (profileEvent && profileEvent->scheduled()) 5145606Snate@binkert.org deschedule(profileEvent); 5159446SAndreas.Sandberg@ARM.com 5169446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 5179446SAndreas.Sandberg@ARM.com // it gets switched in later. 5189446SAndreas.Sandberg@ARM.com flushTLBs(); 519180SN/A} 520180SN/A 521180SN/Avoid 5228737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 523180SN/A{ 5242680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 5259152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 5269430SAndreas.Sandberg@ARM.com assert(_switchedOut); 5279430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 5289332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 5299332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 5309430SAndreas.Sandberg@ARM.com _switchedOut = false; 5315712Shsul@eecs.umich.edu 5326221Snate@binkert.org ThreadID size = threadContexts.size(); 5336221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5342680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 5352680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 536180SN/A 5372680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 5382651Ssaidi@eecs.umich.edu 5392680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 5402651Ssaidi@eecs.umich.edu 5415714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 5425715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 5435714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 5442359SN/A 5455875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 5465875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 5475875Ssteve.reinhardt@amd.com * point. 5485875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 5495217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 5505875Ssteve.reinhardt@amd.com */ 5517781SAli.Saidi@ARM.com 5529294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 5539294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 5549294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 5559294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 5567781SAli.Saidi@ARM.com 5577781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 5589178Sandreas.hansson@arm.com if (new_itb_port) { 5599178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 5607781SAli.Saidi@ARM.com assert(old_itb_port); 5619178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 5629294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 5639178Sandreas.hansson@arm.com old_itb_port->unbind(); 5648922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 5657781SAli.Saidi@ARM.com } 5669178Sandreas.hansson@arm.com if (new_dtb_port) { 5679178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 5687781SAli.Saidi@ARM.com assert(old_dtb_port); 5699178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 5709294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 5719178Sandreas.hansson@arm.com old_dtb_port->unbind(); 5728922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 5737781SAli.Saidi@ARM.com } 57410194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 57510194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 5768733Sgeoffrey.blake@arm.com 5778887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 5788887Sgeoffrey.blake@arm.com // objects over in the switch 5798887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 5808887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 5818887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 5829294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 5838922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 5849294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 5858922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 5869294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 5878922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 5889294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 5898922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 5908733Sgeoffrey.blake@arm.com 59110194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 59210194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 59310194SGeoffrey.Blake@arm.com 5948887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 5959178Sandreas.hansson@arm.com if (new_checker_itb_port) { 5969178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 5978887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 5989178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 5999294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6009294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 6019178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 6028922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 6038887Sgeoffrey.blake@arm.com } 6049178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 6059178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 6068887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 6079178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 6089294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6099294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 6109178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 6118922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 6128887Sgeoffrey.blake@arm.com } 6138733Sgeoffrey.blake@arm.com } 614180SN/A } 615605SN/A 6163520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 61711150Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 61811150Smitch.hayenga@arm.com interrupts[tid]->setCPU(this); 61911150Smitch.hayenga@arm.com } 62011150Smitch.hayenga@arm.com oldCPU->interrupts.clear(); 6212254SN/A 6228779Sgblack@eecs.umich.edu if (FullSystem) { 6238779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 6248779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 6252254SN/A 6268779Sgblack@eecs.umich.edu if (profileEvent) 6278779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 6288779Sgblack@eecs.umich.edu } 6294192Sktlim@umich.edu 6309178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 6319178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 6329178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 6339178Sandreas.hansson@arm.com // we are switching to. 6349178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 6359178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 6369294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 6379178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 6389178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 6394192Sktlim@umich.edu 6409178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 6419178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 6429294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 6439178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 6449178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 645180SN/A} 646180SN/A 6479446SAndreas.Sandberg@ARM.comvoid 6489446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 6499446SAndreas.Sandberg@ARM.com{ 6509446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 6519446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 6529446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 6539446SAndreas.Sandberg@ARM.com 6549446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 6559446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 6569446SAndreas.Sandberg@ARM.com if (checker) { 6579446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 6589446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 6599446SAndreas.Sandberg@ARM.com } 6609446SAndreas.Sandberg@ARM.com } 6619446SAndreas.Sandberg@ARM.com} 6629446SAndreas.Sandberg@ARM.com 66312127Sspwilson2@wisc.eduvoid 66412127Sspwilson2@wisc.eduBaseCPU::processProfileEvent() 66512127Sspwilson2@wisc.edu{ 66612127Sspwilson2@wisc.edu ThreadID size = threadContexts.size(); 667180SN/A 66812127Sspwilson2@wisc.edu for (ThreadID i = 0; i < size; ++i) 66912127Sspwilson2@wisc.edu threadContexts[i]->profileSample(); 6701917SN/A 67112127Sspwilson2@wisc.edu schedule(profileEvent, curTick() + params()->profile); 6721917SN/A} 6731917SN/A 6742SN/Avoid 67510905Sandreas.sandberg@arm.comBaseCPU::serialize(CheckpointOut &cp) const 676921SN/A{ 6774000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 6789332Sdam.sunwoo@arm.com 6799448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6809448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 6819448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 6829448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 6839448SAndreas.Sandberg@ARM.com * system. */ 6849448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 6859332Sdam.sunwoo@arm.com 6869448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 6879448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 68810905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 68911150Smitch.hayenga@arm.com interrupts[i]->serialize(cp); 69010905Sandreas.sandberg@arm.com serializeThread(cp, i); 6919448SAndreas.Sandberg@ARM.com } 6929448SAndreas.Sandberg@ARM.com } 693921SN/A} 694921SN/A 695921SN/Avoid 69610905Sandreas.sandberg@arm.comBaseCPU::unserialize(CheckpointIn &cp) 697921SN/A{ 6984000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 6999448SAndreas.Sandberg@ARM.com 7009448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7019448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 7029448SAndreas.Sandberg@ARM.com 7039448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 70410905Sandreas.sandberg@arm.com for (ThreadID i = 0; i < numThreads; ++i) { 70510905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 70611150Smitch.hayenga@arm.com interrupts[i]->unserialize(cp); 70710905Sandreas.sandberg@arm.com unserializeThread(cp, i); 70810905Sandreas.sandberg@arm.com } 7099448SAndreas.Sandberg@ARM.com } 710921SN/A} 711921SN/A 7121191SN/Avoid 7139749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 7149749Sandreas@sandberg.pp.se{ 7159749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 7169983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7179749Sandreas@sandberg.pp.se 7189749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 7199749Sandreas@sandberg.pp.se} 7209749Sandreas@sandberg.pp.se 72111415SGeoffrey.Blake@arm.comuint64_t 72211415SGeoffrey.Blake@arm.comBaseCPU::getCurrentInstCount(ThreadID tid) 72311415SGeoffrey.Blake@arm.com{ 72411415SGeoffrey.Blake@arm.com return Tick(comInstEventQueue[tid]->getCurTick()); 72511415SGeoffrey.Blake@arm.com} 72611415SGeoffrey.Blake@arm.com 72710529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 72810529Smorr@cs.wisc.edu armed = false; 72910529Smorr@cs.wisc.edu waiting = false; 73010529Smorr@cs.wisc.edu gotWakeup = false; 73110529Smorr@cs.wisc.edu} 73210529Smorr@cs.wisc.edu 73310529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 73410529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 73511321Ssteve.reinhardt@amd.com if (armed && waiting) { 73611321Ssteve.reinhardt@amd.com if (pAddr == pkt->getAddr()) { 73710529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 73810529Smorr@cs.wisc.edu pkt->getAddr()); 73910529Smorr@cs.wisc.edu waiting = false; 74010529Smorr@cs.wisc.edu return true; 74110529Smorr@cs.wisc.edu } 74210529Smorr@cs.wisc.edu } 74310529Smorr@cs.wisc.edu return false; 74410529Smorr@cs.wisc.edu} 74510529Smorr@cs.wisc.edu 7469749Sandreas@sandberg.pp.sevoid 7479749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 7489749Sandreas@sandberg.pp.se{ 7499749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 7509983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7519749Sandreas@sandberg.pp.se 7529749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 7539749Sandreas@sandberg.pp.se} 7549749Sandreas@sandberg.pp.se 7559749Sandreas@sandberg.pp.se 7569749Sandreas@sandberg.pp.sevoid 7571191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 7581191SN/A{ 7591191SN/A if (!debugSymbolTable) 7601191SN/A return; 7611191SN/A 7621191SN/A // if pc enters different function, print new function symbol and 7631191SN/A // update saved range. Otherwise do nothing. 7641191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 7651191SN/A string sym_str; 7661191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 7671191SN/A currentFunctionStart, 7681191SN/A currentFunctionEnd); 7691191SN/A 7701191SN/A if (!found) { 7711191SN/A // no symbol found: use addr as label 7721191SN/A sym_str = csprintf("0x%x", pc); 7731191SN/A currentFunctionStart = pc; 7741191SN/A currentFunctionEnd = pc + 1; 7751191SN/A } 7761191SN/A 7771191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 7787823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 7797823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 7801191SN/A } 7811191SN/A} 78212122Sjose.marinho@arm.com 78312122Sjose.marinho@arm.combool 78412122Sjose.marinho@arm.comBaseCPU::waitForRemoteGDB() const 78512122Sjose.marinho@arm.com{ 78612122Sjose.marinho@arm.com return params()->wait_for_remote_gdb; 78712122Sjose.marinho@arm.com} 788