base.cc revision 11877
12SN/A/* 211526Sdavid.guillen@arm.com * Copyright (c) 2011-2012,2016 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 4811793Sbrandon.potter@amd.com#include "cpu/base.hh" 4911793Sbrandon.potter@amd.com 501388SN/A#include <iostream> 518229Snate@binkert.org#include <sstream> 522SN/A#include <string> 532SN/A 547781SAli.Saidi@ARM.com#include "arch/tlb.hh" 5511793Sbrandon.potter@amd.com#include "base/cprintf.hh" 568229Snate@binkert.org#include "base/loader/symtab.hh" 571191SN/A#include "base/misc.hh" 581388SN/A#include "base/output.hh" 595529Snate@binkert.org#include "base/trace.hh" 6010529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 612651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 628229Snate@binkert.org#include "cpu/profile.hh" 632680Sktlim@umich.edu#include "cpu/thread_context.hh" 6410529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 658232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6610529Smorr@cs.wisc.edu#include "mem/page_table.hh" 675529Snate@binkert.org#include "params/BaseCPU.hh" 6811526Sdavid.guillen@arm.com#include "sim/clocked_object.hh" 698779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 702190SN/A#include "sim/process.hh" 7156SN/A#include "sim/sim_events.hh" 728229Snate@binkert.org#include "sim/sim_exit.hh" 732190SN/A#include "sim/system.hh" 742SN/A 752359SN/A// Hack 762359SN/A#include "sim/stat_control.hh" 772359SN/A 782SN/Ausing namespace std; 792SN/A 802SN/Avector<BaseCPU *> BaseCPU::cpuList; 812SN/A 822SN/A// This variable reflects the max number of threads in any CPU. Be 832SN/A// careful to only use it once all the CPUs that you care about have 842SN/A// been initialized 852SN/Aint maxThreadsPerCPU = 1; 862SN/A 875606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 886144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 896144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 903126Sktlim@umich.edu{ 916144Sksewell@umich.edu if (_interval) 927823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 933126Sktlim@umich.edu} 943126Sktlim@umich.edu 952356SN/Avoid 962356SN/ACPUProgressEvent::process() 972356SN/A{ 988834Satgutier@umich.edu Counter temp = cpu->totalOps(); 9910786Smalek.musleh@gmail.com 10010786Smalek.musleh@gmail.com if (_repeatEvent) 10110786Smalek.musleh@gmail.com cpu->schedule(this, curTick() + _interval); 10210786Smalek.musleh@gmail.com 10311321Ssteve.reinhardt@amd.com if (cpu->switchedOut()) { 10410786Smalek.musleh@gmail.com return; 10510786Smalek.musleh@gmail.com } 10610786Smalek.musleh@gmail.com 1072356SN/A#ifndef NDEBUG 1089179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 1092367SN/A 1106144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1116144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1126144Sksewell@umich.edu ipc); 1132356SN/A ipc = 0.0; 1142367SN/A#else 1156144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1167823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1176144Sksewell@umich.edu temp - lastNumInst); 1182367SN/A#endif 1192356SN/A lastNumInst = temp; 1202356SN/A} 1212356SN/A 1222356SN/Aconst char * 1235336Shines@cs.fsu.eduCPUProgressEvent::description() const 1242356SN/A{ 1254873Sstever@eecs.umich.edu return "CPU Progress"; 1262356SN/A} 1272356SN/A 1288876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12910190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1308832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1318832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 13211050Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 1339814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1349220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 13510529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 13610537Sandreas.hansson@arm.com functionTraceStream(nullptr), currentFunctionStart(0), 13710537Sandreas.hansson@arm.com currentFunctionEnd(0), functionEntryTick(0), 13811877Sbrandon.potter@amd.com addressMonitor(p->numThreads), 13911877Sbrandon.potter@amd.com syscallRetryLatency(p->syscallRetryLatency) 1402SN/A{ 1415712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1425712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1435712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1445712Shsul@eecs.umich.edu } 1455712Shsul@eecs.umich.edu 1462SN/A // add self to global list of CPUs 1472SN/A cpuList.push_back(this); 1482SN/A 14910190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 15010190Sakash.bagdia@arm.com _cpuId, _socketId); 1515712Shsul@eecs.umich.edu 1526221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1536221Snate@binkert.org maxThreadsPerCPU = numThreads; 1542SN/A 1552SN/A // allocate per-thread instruction-based event queues 1566221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1576221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1586221Snate@binkert.org comInstEventQueue[tid] = 1596221Snate@binkert.org new EventQueue("instruction-based event queue"); 1602SN/A 1612SN/A // 1622SN/A // set up instruction-count-based termination events, if any 1632SN/A // 1645606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1655606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1669749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1679749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1685606Snate@binkert.org } 1692SN/A 1709647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1719647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1729647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1739647Sdam.sunwoo@arm.com // exitting the simulation loop. 1749647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1759647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1769749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1779749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1789647Sdam.sunwoo@arm.com } 1799647Sdam.sunwoo@arm.com 1801400SN/A if (p->max_insts_all_threads != 0) { 1815606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1825606Snate@binkert.org 1832SN/A // allocate & initialize shared downcounter: each event will 1842SN/A // decrement this when triggered; simulation will terminate 1852SN/A // when counter reaches 0 1862SN/A int *counter = new int; 1876221Snate@binkert.org *counter = numThreads; 1886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1895606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1906670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1915606Snate@binkert.org } 1922SN/A } 1932SN/A 194124SN/A // allocate per-thread load-based event queues 1956221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1976221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 198124SN/A 199124SN/A // 200124SN/A // set up instruction-count-based termination events, if any 201124SN/A // 2025606Snate@binkert.org if (p->max_loads_any_thread != 0) { 2035606Snate@binkert.org const char *cause = "a thread reached the max load count"; 2049749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 2059749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 2065606Snate@binkert.org } 207124SN/A 2081400SN/A if (p->max_loads_all_threads != 0) { 2095606Snate@binkert.org const char *cause = "all threads reached the max load count"; 210124SN/A // allocate & initialize shared downcounter: each event will 211124SN/A // decrement this when triggered; simulation will terminate 212124SN/A // when counter reaches 0 213124SN/A int *counter = new int; 2146221Snate@binkert.org *counter = numThreads; 2156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2165606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2176221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2185606Snate@binkert.org } 219124SN/A } 220124SN/A 2211191SN/A functionTracingEnabled = false; 2225529Snate@binkert.org if (p->function_trace) { 2238634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 22411359Sandreas@sandberg.pp.se functionTraceStream = simout.findOrCreate(fname)->stream(); 2258634Schris.emmons@arm.com 2261191SN/A currentFunctionStart = currentFunctionEnd = 0; 2275529Snate@binkert.org functionEntryTick = p->function_trace_start; 2281191SN/A 2295529Snate@binkert.org if (p->function_trace_start == 0) { 2301191SN/A functionTracingEnabled = true; 2311191SN/A } else { 2325606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2335606Snate@binkert.org Event *event = new wrap(this, true); 2345606Snate@binkert.org schedule(event, p->function_trace_start); 2351191SN/A } 2361191SN/A } 2378876Sandreas.hansson@arm.com 2388876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2398876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2409433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 24111221Sandreas.sandberg@arm.com fatal_if(interrupts.size() != numThreads, 24211221Sandreas.sandberg@arm.com "CPU %s has %i interrupt controllers, but is expecting one " 24311221Sandreas.sandberg@arm.com "per thread (%i)\n", 24411221Sandreas.sandberg@arm.com name(), interrupts.size(), numThreads); 24511221Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 24611221Sandreas.sandberg@arm.com interrupts[tid]->setCPU(this); 2478876Sandreas.hansson@arm.com } 2485810Sgblack@eecs.umich.edu 2498779Sgblack@eecs.umich.edu if (FullSystem) { 2508779Sgblack@eecs.umich.edu if (params()->profile) 2518779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2528779Sgblack@eecs.umich.edu } 2535529Snate@binkert.org tracer = params()->tracer; 2549384SAndreas.Sandberg@arm.com 2559384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2569384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2579384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2589384SAndreas.Sandberg@arm.com } 2591917SN/A} 2601191SN/A 2611191SN/Avoid 2621191SN/ABaseCPU::enableFunctionTrace() 2631191SN/A{ 2641191SN/A functionTracingEnabled = true; 2651191SN/A} 2661191SN/A 2671191SN/ABaseCPU::~BaseCPU() 2681191SN/A{ 2699086Sandreas.hansson@arm.com delete profileEvent; 2709086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2719086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2721191SN/A} 2731191SN/A 2741129SN/Avoid 27511148Smitch.hayenga@arm.comBaseCPU::armMonitor(ThreadID tid, Addr address) 27610529Smorr@cs.wisc.edu{ 27711148Smitch.hayenga@arm.com assert(tid < numThreads); 27811148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 27911148Smitch.hayenga@arm.com 28011148Smitch.hayenga@arm.com monitor.armed = true; 28111148Smitch.hayenga@arm.com monitor.vAddr = address; 28211148Smitch.hayenga@arm.com monitor.pAddr = 0x0; 28311148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 28410529Smorr@cs.wisc.edu} 28510529Smorr@cs.wisc.edu 28610529Smorr@cs.wisc.edubool 28711148Smitch.hayenga@arm.comBaseCPU::mwait(ThreadID tid, PacketPtr pkt) 28810529Smorr@cs.wisc.edu{ 28911148Smitch.hayenga@arm.com assert(tid < numThreads); 29011148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 29111148Smitch.hayenga@arm.com 29211325Ssteve.reinhardt@amd.com if (!monitor.gotWakeup) { 29310529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 29410529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 29510529Smorr@cs.wisc.edu 29610529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 29711148Smitch.hayenga@arm.com monitor.pAddr = pkt->getAddr() & mask; 29811148Smitch.hayenga@arm.com monitor.waiting = true; 29910529Smorr@cs.wisc.edu 30011148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 30111148Smitch.hayenga@arm.com "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 30210529Smorr@cs.wisc.edu return true; 30310529Smorr@cs.wisc.edu } else { 30411148Smitch.hayenga@arm.com monitor.gotWakeup = false; 30510529Smorr@cs.wisc.edu return false; 30610529Smorr@cs.wisc.edu } 30710529Smorr@cs.wisc.edu} 30810529Smorr@cs.wisc.edu 30910529Smorr@cs.wisc.eduvoid 31011148Smitch.hayenga@arm.comBaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb) 31110529Smorr@cs.wisc.edu{ 31211148Smitch.hayenga@arm.com assert(tid < numThreads); 31311148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 31411148Smitch.hayenga@arm.com 31510529Smorr@cs.wisc.edu Request req; 31611148Smitch.hayenga@arm.com Addr addr = monitor.vAddr; 31710529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 31810529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 31910529Smorr@cs.wisc.edu int size = block_size; 32010529Smorr@cs.wisc.edu 32110529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 32210529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 32310529Smorr@cs.wisc.edu 32410529Smorr@cs.wisc.edu if (secondAddr > addr) 32510529Smorr@cs.wisc.edu size = secondAddr - addr; 32610529Smorr@cs.wisc.edu 32710529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 32810529Smorr@cs.wisc.edu 32910529Smorr@cs.wisc.edu // translate to physical address 33010529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 33110529Smorr@cs.wisc.edu assert(fault == NoFault); 33210529Smorr@cs.wisc.edu 33311148Smitch.hayenga@arm.com monitor.pAddr = req.getPaddr() & mask; 33411148Smitch.hayenga@arm.com monitor.waiting = true; 33510529Smorr@cs.wisc.edu 33611148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 33711148Smitch.hayenga@arm.com tid, monitor.vAddr, monitor.pAddr); 33810529Smorr@cs.wisc.edu} 33910529Smorr@cs.wisc.edu 34010529Smorr@cs.wisc.eduvoid 3411129SN/ABaseCPU::init() 3421129SN/A{ 3439523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3442680Sktlim@umich.edu registerThreadContexts(); 3459523SAndreas.Sandberg@ARM.com 3469523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3479523SAndreas.Sandberg@ARM.com } 3481129SN/A} 349180SN/A 3502SN/Avoid 3511917SN/ABaseCPU::startup() 3521917SN/A{ 3538779Sgblack@eecs.umich.edu if (FullSystem) { 3549433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3558779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3568779Sgblack@eecs.umich.edu } 3572356SN/A 3585529Snate@binkert.org if (params()->progress_interval) { 3599179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3602356SN/A } 36111526Sdavid.guillen@arm.com 36211526Sdavid.guillen@arm.com // Assumption CPU start to operate instantaneously without any latency 36311526Sdavid.guillen@arm.com if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED) 36411526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 36511526Sdavid.guillen@arm.com 3661917SN/A} 3671917SN/A 36810464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 36910464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 37010464SAndreas.Sandberg@ARM.com{ 37110464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 37210464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 37310464SAndreas.Sandberg@ARM.com 37410464SAndreas.Sandberg@ARM.com return ptr; 37510464SAndreas.Sandberg@ARM.com} 37610464SAndreas.Sandberg@ARM.com 37710464SAndreas.Sandberg@ARM.comvoid 37810464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 37910464SAndreas.Sandberg@ARM.com{ 38010464SAndreas.Sandberg@ARM.com ppCycles = pmuProbePoint("Cycles"); 38110464SAndreas.Sandberg@ARM.com 38210464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 38310464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 38410464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 38510464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 38610464SAndreas.Sandberg@ARM.com} 38710464SAndreas.Sandberg@ARM.com 38810464SAndreas.Sandberg@ARM.comvoid 38910464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 39010464SAndreas.Sandberg@ARM.com{ 39110464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 39210464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 39310464SAndreas.Sandberg@ARM.com 39410464SAndreas.Sandberg@ARM.com 39510464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 39610464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 39710464SAndreas.Sandberg@ARM.com 39810464SAndreas.Sandberg@ARM.com if (inst->isStore()) 39910643Snikos.nikoleris@gmail.com ppRetiredStores->notify(1); 40010464SAndreas.Sandberg@ARM.com 40110464SAndreas.Sandberg@ARM.com if (inst->isControl()) 40210464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 40310464SAndreas.Sandberg@ARM.com} 4041917SN/A 4051917SN/Avoid 4062SN/ABaseCPU::regStats() 4072SN/A{ 40811522Sstephan.diestelhorst@arm.com MemObject::regStats(); 40911522Sstephan.diestelhorst@arm.com 410729SN/A using namespace Stats; 411707SN/A 412707SN/A numCycles 413707SN/A .name(name() + ".numCycles") 414707SN/A .desc("number of cpu cycles simulated") 415707SN/A ; 416707SN/A 4177914SBrad.Beckmann@amd.com numWorkItemsStarted 4187914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 4197914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 4207914SBrad.Beckmann@amd.com ; 4217914SBrad.Beckmann@amd.com 4227914SBrad.Beckmann@amd.com numWorkItemsCompleted 4237914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4247914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4257914SBrad.Beckmann@amd.com ; 4267914SBrad.Beckmann@amd.com 4272680Sktlim@umich.edu int size = threadContexts.size(); 4282SN/A if (size > 1) { 4292SN/A for (int i = 0; i < size; ++i) { 4302SN/A stringstream namestr; 4312SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4322680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4332SN/A } 4342SN/A } else if (size == 1) 4352680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4362SN/A} 4372SN/A 4389294Sandreas.hansson@arm.comBaseMasterPort & 4399294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4408850Sandreas.hansson@arm.com{ 4418850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4428850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4438850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4449608Sandreas.hansson@arm.com // return a MasterPort pointer. 4458850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4468922Swilliam.wang@arm.com return getDataPort(); 4478850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4488922Swilliam.wang@arm.com return getInstPort(); 4498850Sandreas.hansson@arm.com else 4508922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4518850Sandreas.hansson@arm.com} 4528850Sandreas.hansson@arm.com 453180SN/Avoid 4542680Sktlim@umich.eduBaseCPU::registerThreadContexts() 455180SN/A{ 45611146Smitch.hayenga@arm.com assert(system->multiThread || numThreads == 1); 45711146Smitch.hayenga@arm.com 4586221Snate@binkert.org ThreadID size = threadContexts.size(); 4596221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4606221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4612378SN/A 46211146Smitch.hayenga@arm.com if (system->multiThread) { 46311146Smitch.hayenga@arm.com tc->setContextId(system->registerThreadContext(tc)); 46411146Smitch.hayenga@arm.com } else { 4655718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 46611146Smitch.hayenga@arm.com } 4678779Sgblack@eecs.umich.edu 4688779Sgblack@eecs.umich.edu if (!FullSystem) 4698779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 470180SN/A } 471180SN/A} 472180SN/A 473180SN/A 4744000Ssaidi@eecs.umich.eduint 4754000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 4764000Ssaidi@eecs.umich.edu{ 4776221Snate@binkert.org ThreadID size = threadContexts.size(); 4786221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4796221Snate@binkert.org if (tc == threadContexts[tid]) 4806221Snate@binkert.org return tid; 4814000Ssaidi@eecs.umich.edu } 4824000Ssaidi@eecs.umich.edu return 0; 4834000Ssaidi@eecs.umich.edu} 4844000Ssaidi@eecs.umich.edu 485180SN/Avoid 48611526Sdavid.guillen@arm.comBaseCPU::activateContext(ThreadID thread_num) 48711526Sdavid.guillen@arm.com{ 48811526Sdavid.guillen@arm.com // For any active thread running, update CPU power state to active (ON) 48911526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 49011526Sdavid.guillen@arm.com} 49111526Sdavid.guillen@arm.com 49211526Sdavid.guillen@arm.comvoid 49311526Sdavid.guillen@arm.comBaseCPU::suspendContext(ThreadID thread_num) 49411526Sdavid.guillen@arm.com{ 49511526Sdavid.guillen@arm.com // Check if all threads are suspended 49611526Sdavid.guillen@arm.com for (auto t : threadContexts) { 49711526Sdavid.guillen@arm.com if (t->status() != ThreadContext::Suspended) { 49811526Sdavid.guillen@arm.com return; 49911526Sdavid.guillen@arm.com } 50011526Sdavid.guillen@arm.com } 50111526Sdavid.guillen@arm.com 50211526Sdavid.guillen@arm.com // All CPU threads suspended, enter lower power state for the CPU 50311526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::CLK_GATED); 50411526Sdavid.guillen@arm.com} 50511526Sdavid.guillen@arm.com 50611526Sdavid.guillen@arm.comvoid 5072798Sktlim@umich.eduBaseCPU::switchOut() 508180SN/A{ 5099430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 5109430SAndreas.Sandberg@ARM.com _switchedOut = true; 5112359SN/A if (profileEvent && profileEvent->scheduled()) 5125606Snate@binkert.org deschedule(profileEvent); 5139446SAndreas.Sandberg@ARM.com 5149446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 5159446SAndreas.Sandberg@ARM.com // it gets switched in later. 5169446SAndreas.Sandberg@ARM.com flushTLBs(); 517180SN/A} 518180SN/A 519180SN/Avoid 5208737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 521180SN/A{ 5222680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 5239152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 5249430SAndreas.Sandberg@ARM.com assert(_switchedOut); 5259430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 5269332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 5279332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 5289430SAndreas.Sandberg@ARM.com _switchedOut = false; 5295712Shsul@eecs.umich.edu 5306221Snate@binkert.org ThreadID size = threadContexts.size(); 5316221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5322680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 5332680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 534180SN/A 5352680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 5362651Ssaidi@eecs.umich.edu 5372680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 5382651Ssaidi@eecs.umich.edu 5395714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 5405715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 5415714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 5422359SN/A 5435875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 5445875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 5455875Ssteve.reinhardt@amd.com * point. 5465875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 5475217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 5485875Ssteve.reinhardt@amd.com */ 5497781SAli.Saidi@ARM.com 5509294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 5519294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 5529294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 5539294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 5547781SAli.Saidi@ARM.com 5557781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 5569178Sandreas.hansson@arm.com if (new_itb_port) { 5579178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 5587781SAli.Saidi@ARM.com assert(old_itb_port); 5599178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 5609294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 5619178Sandreas.hansson@arm.com old_itb_port->unbind(); 5628922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 5637781SAli.Saidi@ARM.com } 5649178Sandreas.hansson@arm.com if (new_dtb_port) { 5659178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 5667781SAli.Saidi@ARM.com assert(old_dtb_port); 5679178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 5689294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 5699178Sandreas.hansson@arm.com old_dtb_port->unbind(); 5708922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 5717781SAli.Saidi@ARM.com } 57210194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 57310194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 5748733Sgeoffrey.blake@arm.com 5758887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 5768887Sgeoffrey.blake@arm.com // objects over in the switch 5778887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 5788887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 5798887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 5809294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 5818922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 5829294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 5838922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 5849294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 5858922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 5869294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 5878922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 5888733Sgeoffrey.blake@arm.com 58910194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 59010194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 59110194SGeoffrey.Blake@arm.com 5928887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 5939178Sandreas.hansson@arm.com if (new_checker_itb_port) { 5949178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 5958887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 5969178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 5979294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 5989294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 5999178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 6008922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 6018887Sgeoffrey.blake@arm.com } 6029178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 6039178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 6048887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 6059178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 6069294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6079294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 6089178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 6098922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 6108887Sgeoffrey.blake@arm.com } 6118733Sgeoffrey.blake@arm.com } 612180SN/A } 613605SN/A 6143520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 61511150Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 61611150Smitch.hayenga@arm.com interrupts[tid]->setCPU(this); 61711150Smitch.hayenga@arm.com } 61811150Smitch.hayenga@arm.com oldCPU->interrupts.clear(); 6192254SN/A 6208779Sgblack@eecs.umich.edu if (FullSystem) { 6218779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 6228779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 6232254SN/A 6248779Sgblack@eecs.umich.edu if (profileEvent) 6258779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 6268779Sgblack@eecs.umich.edu } 6274192Sktlim@umich.edu 6289178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 6299178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 6309178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 6319178Sandreas.hansson@arm.com // we are switching to. 6329178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 6339178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 6349294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 6359178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 6369178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 6374192Sktlim@umich.edu 6389178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 6399178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 6409294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 6419178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 6429178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 643180SN/A} 644180SN/A 6459446SAndreas.Sandberg@ARM.comvoid 6469446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 6479446SAndreas.Sandberg@ARM.com{ 6489446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 6499446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 6509446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 6519446SAndreas.Sandberg@ARM.com 6529446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 6539446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 6549446SAndreas.Sandberg@ARM.com if (checker) { 6559446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 6569446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 6579446SAndreas.Sandberg@ARM.com } 6589446SAndreas.Sandberg@ARM.com } 6599446SAndreas.Sandberg@ARM.com} 6609446SAndreas.Sandberg@ARM.com 661180SN/A 6625536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 6635606Snate@binkert.org : cpu(_cpu), interval(_interval) 6641917SN/A{ } 6651917SN/A 6661917SN/Avoid 6671917SN/ABaseCPU::ProfileEvent::process() 6681917SN/A{ 6696221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 6706221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 6712680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 6722680Sktlim@umich.edu tc->profileSample(); 6731917SN/A } 6742254SN/A 6757823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 6761917SN/A} 6771917SN/A 6782SN/Avoid 67910905Sandreas.sandberg@arm.comBaseCPU::serialize(CheckpointOut &cp) const 680921SN/A{ 6814000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 6829332Sdam.sunwoo@arm.com 6839448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6849448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 6859448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 6869448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 6879448SAndreas.Sandberg@ARM.com * system. */ 6889448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 6899332Sdam.sunwoo@arm.com 6909448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 6919448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 69210905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 69311150Smitch.hayenga@arm.com interrupts[i]->serialize(cp); 69410905Sandreas.sandberg@arm.com serializeThread(cp, i); 6959448SAndreas.Sandberg@ARM.com } 6969448SAndreas.Sandberg@ARM.com } 697921SN/A} 698921SN/A 699921SN/Avoid 70010905Sandreas.sandberg@arm.comBaseCPU::unserialize(CheckpointIn &cp) 701921SN/A{ 7024000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 7039448SAndreas.Sandberg@ARM.com 7049448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7059448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 7069448SAndreas.Sandberg@ARM.com 7079448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 70810905Sandreas.sandberg@arm.com for (ThreadID i = 0; i < numThreads; ++i) { 70910905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 71011150Smitch.hayenga@arm.com interrupts[i]->unserialize(cp); 71110905Sandreas.sandberg@arm.com unserializeThread(cp, i); 71210905Sandreas.sandberg@arm.com } 7139448SAndreas.Sandberg@ARM.com } 714921SN/A} 715921SN/A 7161191SN/Avoid 7179749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 7189749Sandreas@sandberg.pp.se{ 7199749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 7209983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7219749Sandreas@sandberg.pp.se 7229749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 7239749Sandreas@sandberg.pp.se} 7249749Sandreas@sandberg.pp.se 72511415SGeoffrey.Blake@arm.comuint64_t 72611415SGeoffrey.Blake@arm.comBaseCPU::getCurrentInstCount(ThreadID tid) 72711415SGeoffrey.Blake@arm.com{ 72811415SGeoffrey.Blake@arm.com return Tick(comInstEventQueue[tid]->getCurTick()); 72911415SGeoffrey.Blake@arm.com} 73011415SGeoffrey.Blake@arm.com 73110529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 73210529Smorr@cs.wisc.edu armed = false; 73310529Smorr@cs.wisc.edu waiting = false; 73410529Smorr@cs.wisc.edu gotWakeup = false; 73510529Smorr@cs.wisc.edu} 73610529Smorr@cs.wisc.edu 73710529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 73810529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 73911321Ssteve.reinhardt@amd.com if (armed && waiting) { 74011321Ssteve.reinhardt@amd.com if (pAddr == pkt->getAddr()) { 74110529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 74210529Smorr@cs.wisc.edu pkt->getAddr()); 74310529Smorr@cs.wisc.edu waiting = false; 74410529Smorr@cs.wisc.edu return true; 74510529Smorr@cs.wisc.edu } 74610529Smorr@cs.wisc.edu } 74710529Smorr@cs.wisc.edu return false; 74810529Smorr@cs.wisc.edu} 74910529Smorr@cs.wisc.edu 7509749Sandreas@sandberg.pp.sevoid 7519749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 7529749Sandreas@sandberg.pp.se{ 7539749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 7549983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7559749Sandreas@sandberg.pp.se 7569749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 7579749Sandreas@sandberg.pp.se} 7589749Sandreas@sandberg.pp.se 7599749Sandreas@sandberg.pp.se 7609749Sandreas@sandberg.pp.sevoid 7611191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 7621191SN/A{ 7631191SN/A if (!debugSymbolTable) 7641191SN/A return; 7651191SN/A 7661191SN/A // if pc enters different function, print new function symbol and 7671191SN/A // update saved range. Otherwise do nothing. 7681191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 7691191SN/A string sym_str; 7701191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 7711191SN/A currentFunctionStart, 7721191SN/A currentFunctionEnd); 7731191SN/A 7741191SN/A if (!found) { 7751191SN/A // no symbol found: use addr as label 7761191SN/A sym_str = csprintf("0x%x", pc); 7771191SN/A currentFunctionStart = pc; 7781191SN/A currentFunctionEnd = pc + 1; 7791191SN/A } 7801191SN/A 7811191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 7827823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 7837823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 7841191SN/A } 7851191SN/A} 786