base.cc revision 11325
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 481388SN/A#include <iostream> 498229Snate@binkert.org#include <sstream> 502SN/A#include <string> 512SN/A 527781SAli.Saidi@ARM.com#include "arch/tlb.hh" 538229Snate@binkert.org#include "base/loader/symtab.hh" 541191SN/A#include "base/cprintf.hh" 551191SN/A#include "base/misc.hh" 561388SN/A#include "base/output.hh" 575529Snate@binkert.org#include "base/trace.hh" 5810529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 591717SN/A#include "cpu/base.hh" 602651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 618229Snate@binkert.org#include "cpu/profile.hh" 622680Sktlim@umich.edu#include "cpu/thread_context.hh" 6310529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 648232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6510529Smorr@cs.wisc.edu#include "mem/page_table.hh" 665529Snate@binkert.org#include "params/BaseCPU.hh" 678779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 682190SN/A#include "sim/process.hh" 6956SN/A#include "sim/sim_events.hh" 708229Snate@binkert.org#include "sim/sim_exit.hh" 712190SN/A#include "sim/system.hh" 722SN/A 732359SN/A// Hack 742359SN/A#include "sim/stat_control.hh" 752359SN/A 762SN/Ausing namespace std; 772SN/A 782SN/Avector<BaseCPU *> BaseCPU::cpuList; 792SN/A 802SN/A// This variable reflects the max number of threads in any CPU. Be 812SN/A// careful to only use it once all the CPUs that you care about have 822SN/A// been initialized 832SN/Aint maxThreadsPerCPU = 1; 842SN/A 855606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 866144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 876144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 883126Sktlim@umich.edu{ 896144Sksewell@umich.edu if (_interval) 907823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 913126Sktlim@umich.edu} 923126Sktlim@umich.edu 932356SN/Avoid 942356SN/ACPUProgressEvent::process() 952356SN/A{ 968834Satgutier@umich.edu Counter temp = cpu->totalOps(); 9710786Smalek.musleh@gmail.com 9810786Smalek.musleh@gmail.com if (_repeatEvent) 9910786Smalek.musleh@gmail.com cpu->schedule(this, curTick() + _interval); 10010786Smalek.musleh@gmail.com 10111321Ssteve.reinhardt@amd.com if (cpu->switchedOut()) { 10210786Smalek.musleh@gmail.com return; 10310786Smalek.musleh@gmail.com } 10410786Smalek.musleh@gmail.com 1052356SN/A#ifndef NDEBUG 1069179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 1072367SN/A 1086144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1096144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1106144Sksewell@umich.edu ipc); 1112356SN/A ipc = 0.0; 1122367SN/A#else 1136144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1147823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1156144Sksewell@umich.edu temp - lastNumInst); 1162367SN/A#endif 1172356SN/A lastNumInst = temp; 1182356SN/A} 1192356SN/A 1202356SN/Aconst char * 1215336Shines@cs.fsu.eduCPUProgressEvent::description() const 1222356SN/A{ 1234873Sstever@eecs.umich.edu return "CPU Progress"; 1242356SN/A} 1252356SN/A 1268876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12710190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1288832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1298832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 13011050Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 1319814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1329220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 13310529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 13410537Sandreas.hansson@arm.com functionTraceStream(nullptr), currentFunctionStart(0), 13510537Sandreas.hansson@arm.com currentFunctionEnd(0), functionEntryTick(0), 13611148Smitch.hayenga@arm.com addressMonitor(p->numThreads) 1372SN/A{ 1385712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1395712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1405712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1415712Shsul@eecs.umich.edu } 1425712Shsul@eecs.umich.edu 1432SN/A // add self to global list of CPUs 1442SN/A cpuList.push_back(this); 1452SN/A 14610190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 14710190Sakash.bagdia@arm.com _cpuId, _socketId); 1485712Shsul@eecs.umich.edu 1496221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1506221Snate@binkert.org maxThreadsPerCPU = numThreads; 1512SN/A 1522SN/A // allocate per-thread instruction-based event queues 1536221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1556221Snate@binkert.org comInstEventQueue[tid] = 1566221Snate@binkert.org new EventQueue("instruction-based event queue"); 1572SN/A 1582SN/A // 1592SN/A // set up instruction-count-based termination events, if any 1602SN/A // 1615606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1625606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1639749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1649749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1655606Snate@binkert.org } 1662SN/A 1679647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1689647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1699647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1709647Sdam.sunwoo@arm.com // exitting the simulation loop. 1719647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1729647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1739749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1749749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1759647Sdam.sunwoo@arm.com } 1769647Sdam.sunwoo@arm.com 1771400SN/A if (p->max_insts_all_threads != 0) { 1785606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1795606Snate@binkert.org 1802SN/A // allocate & initialize shared downcounter: each event will 1812SN/A // decrement this when triggered; simulation will terminate 1822SN/A // when counter reaches 0 1832SN/A int *counter = new int; 1846221Snate@binkert.org *counter = numThreads; 1856221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1865606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1876670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1885606Snate@binkert.org } 1892SN/A } 1902SN/A 191124SN/A // allocate per-thread load-based event queues 1926221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1936221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1946221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 195124SN/A 196124SN/A // 197124SN/A // set up instruction-count-based termination events, if any 198124SN/A // 1995606Snate@binkert.org if (p->max_loads_any_thread != 0) { 2005606Snate@binkert.org const char *cause = "a thread reached the max load count"; 2019749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 2029749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 2035606Snate@binkert.org } 204124SN/A 2051400SN/A if (p->max_loads_all_threads != 0) { 2065606Snate@binkert.org const char *cause = "all threads reached the max load count"; 207124SN/A // allocate & initialize shared downcounter: each event will 208124SN/A // decrement this when triggered; simulation will terminate 209124SN/A // when counter reaches 0 210124SN/A int *counter = new int; 2116221Snate@binkert.org *counter = numThreads; 2126221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2135606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2146221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2155606Snate@binkert.org } 216124SN/A } 217124SN/A 2181191SN/A functionTracingEnabled = false; 2195529Snate@binkert.org if (p->function_trace) { 2208634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2218634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2228634Schris.emmons@arm.com if (!functionTraceStream) 2238634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2248634Schris.emmons@arm.com 2251191SN/A currentFunctionStart = currentFunctionEnd = 0; 2265529Snate@binkert.org functionEntryTick = p->function_trace_start; 2271191SN/A 2285529Snate@binkert.org if (p->function_trace_start == 0) { 2291191SN/A functionTracingEnabled = true; 2301191SN/A } else { 2315606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2325606Snate@binkert.org Event *event = new wrap(this, true); 2335606Snate@binkert.org schedule(event, p->function_trace_start); 2341191SN/A } 2351191SN/A } 2368876Sandreas.hansson@arm.com 2378876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2388876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2399433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 24011221Sandreas.sandberg@arm.com fatal_if(interrupts.size() != numThreads, 24111221Sandreas.sandberg@arm.com "CPU %s has %i interrupt controllers, but is expecting one " 24211221Sandreas.sandberg@arm.com "per thread (%i)\n", 24311221Sandreas.sandberg@arm.com name(), interrupts.size(), numThreads); 24411221Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 24511221Sandreas.sandberg@arm.com interrupts[tid]->setCPU(this); 2468876Sandreas.hansson@arm.com } 2475810Sgblack@eecs.umich.edu 2488779Sgblack@eecs.umich.edu if (FullSystem) { 2498779Sgblack@eecs.umich.edu if (params()->profile) 2508779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2518779Sgblack@eecs.umich.edu } 2525529Snate@binkert.org tracer = params()->tracer; 2539384SAndreas.Sandberg@arm.com 2549384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2559384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2569384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2579384SAndreas.Sandberg@arm.com } 2581917SN/A} 2591191SN/A 2601191SN/Avoid 2611191SN/ABaseCPU::enableFunctionTrace() 2621191SN/A{ 2631191SN/A functionTracingEnabled = true; 2641191SN/A} 2651191SN/A 2661191SN/ABaseCPU::~BaseCPU() 2671191SN/A{ 2689086Sandreas.hansson@arm.com delete profileEvent; 2699086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2709086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2711191SN/A} 2721191SN/A 2731129SN/Avoid 27411148Smitch.hayenga@arm.comBaseCPU::armMonitor(ThreadID tid, Addr address) 27510529Smorr@cs.wisc.edu{ 27611148Smitch.hayenga@arm.com assert(tid < numThreads); 27711148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 27811148Smitch.hayenga@arm.com 27911148Smitch.hayenga@arm.com monitor.armed = true; 28011148Smitch.hayenga@arm.com monitor.vAddr = address; 28111148Smitch.hayenga@arm.com monitor.pAddr = 0x0; 28211148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 28310529Smorr@cs.wisc.edu} 28410529Smorr@cs.wisc.edu 28510529Smorr@cs.wisc.edubool 28611148Smitch.hayenga@arm.comBaseCPU::mwait(ThreadID tid, PacketPtr pkt) 28710529Smorr@cs.wisc.edu{ 28811148Smitch.hayenga@arm.com assert(tid < numThreads); 28911148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 29011148Smitch.hayenga@arm.com 29111325Ssteve.reinhardt@amd.com if (!monitor.gotWakeup) { 29210529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 29310529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 29410529Smorr@cs.wisc.edu 29510529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 29611148Smitch.hayenga@arm.com monitor.pAddr = pkt->getAddr() & mask; 29711148Smitch.hayenga@arm.com monitor.waiting = true; 29810529Smorr@cs.wisc.edu 29911148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 30011148Smitch.hayenga@arm.com "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 30110529Smorr@cs.wisc.edu return true; 30210529Smorr@cs.wisc.edu } else { 30311148Smitch.hayenga@arm.com monitor.gotWakeup = false; 30410529Smorr@cs.wisc.edu return false; 30510529Smorr@cs.wisc.edu } 30610529Smorr@cs.wisc.edu} 30710529Smorr@cs.wisc.edu 30810529Smorr@cs.wisc.eduvoid 30911148Smitch.hayenga@arm.comBaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb) 31010529Smorr@cs.wisc.edu{ 31111148Smitch.hayenga@arm.com assert(tid < numThreads); 31211148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 31311148Smitch.hayenga@arm.com 31410529Smorr@cs.wisc.edu Request req; 31511148Smitch.hayenga@arm.com Addr addr = monitor.vAddr; 31610529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 31710529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 31810529Smorr@cs.wisc.edu int size = block_size; 31910529Smorr@cs.wisc.edu 32010529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 32110529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 32210529Smorr@cs.wisc.edu 32310529Smorr@cs.wisc.edu if (secondAddr > addr) 32410529Smorr@cs.wisc.edu size = secondAddr - addr; 32510529Smorr@cs.wisc.edu 32610529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 32710529Smorr@cs.wisc.edu 32810529Smorr@cs.wisc.edu // translate to physical address 32910529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 33010529Smorr@cs.wisc.edu assert(fault == NoFault); 33110529Smorr@cs.wisc.edu 33211148Smitch.hayenga@arm.com monitor.pAddr = req.getPaddr() & mask; 33311148Smitch.hayenga@arm.com monitor.waiting = true; 33410529Smorr@cs.wisc.edu 33511148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 33611148Smitch.hayenga@arm.com tid, monitor.vAddr, monitor.pAddr); 33710529Smorr@cs.wisc.edu} 33810529Smorr@cs.wisc.edu 33910529Smorr@cs.wisc.eduvoid 3401129SN/ABaseCPU::init() 3411129SN/A{ 3429523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3432680Sktlim@umich.edu registerThreadContexts(); 3449523SAndreas.Sandberg@ARM.com 3459523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3469523SAndreas.Sandberg@ARM.com } 3471129SN/A} 348180SN/A 3492SN/Avoid 3501917SN/ABaseCPU::startup() 3511917SN/A{ 3528779Sgblack@eecs.umich.edu if (FullSystem) { 3539433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3548779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3558779Sgblack@eecs.umich.edu } 3562356SN/A 3575529Snate@binkert.org if (params()->progress_interval) { 3589179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3592356SN/A } 3601917SN/A} 3611917SN/A 36210464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 36310464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 36410464SAndreas.Sandberg@ARM.com{ 36510464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 36610464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 36710464SAndreas.Sandberg@ARM.com 36810464SAndreas.Sandberg@ARM.com return ptr; 36910464SAndreas.Sandberg@ARM.com} 37010464SAndreas.Sandberg@ARM.com 37110464SAndreas.Sandberg@ARM.comvoid 37210464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 37310464SAndreas.Sandberg@ARM.com{ 37410464SAndreas.Sandberg@ARM.com ppCycles = pmuProbePoint("Cycles"); 37510464SAndreas.Sandberg@ARM.com 37610464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 37710464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 37810464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 37910464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 38010464SAndreas.Sandberg@ARM.com} 38110464SAndreas.Sandberg@ARM.com 38210464SAndreas.Sandberg@ARM.comvoid 38310464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 38410464SAndreas.Sandberg@ARM.com{ 38510464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 38610464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 38710464SAndreas.Sandberg@ARM.com 38810464SAndreas.Sandberg@ARM.com 38910464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 39010464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 39110464SAndreas.Sandberg@ARM.com 39210464SAndreas.Sandberg@ARM.com if (inst->isStore()) 39310643Snikos.nikoleris@gmail.com ppRetiredStores->notify(1); 39410464SAndreas.Sandberg@ARM.com 39510464SAndreas.Sandberg@ARM.com if (inst->isControl()) 39610464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 39710464SAndreas.Sandberg@ARM.com} 3981917SN/A 3991917SN/Avoid 4002SN/ABaseCPU::regStats() 4012SN/A{ 402729SN/A using namespace Stats; 403707SN/A 404707SN/A numCycles 405707SN/A .name(name() + ".numCycles") 406707SN/A .desc("number of cpu cycles simulated") 407707SN/A ; 408707SN/A 4097914SBrad.Beckmann@amd.com numWorkItemsStarted 4107914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 4117914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 4127914SBrad.Beckmann@amd.com ; 4137914SBrad.Beckmann@amd.com 4147914SBrad.Beckmann@amd.com numWorkItemsCompleted 4157914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4167914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4177914SBrad.Beckmann@amd.com ; 4187914SBrad.Beckmann@amd.com 4192680Sktlim@umich.edu int size = threadContexts.size(); 4202SN/A if (size > 1) { 4212SN/A for (int i = 0; i < size; ++i) { 4222SN/A stringstream namestr; 4232SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4242680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4252SN/A } 4262SN/A } else if (size == 1) 4272680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4282SN/A} 4292SN/A 4309294Sandreas.hansson@arm.comBaseMasterPort & 4319294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4328850Sandreas.hansson@arm.com{ 4338850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4348850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4358850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4369608Sandreas.hansson@arm.com // return a MasterPort pointer. 4378850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4388922Swilliam.wang@arm.com return getDataPort(); 4398850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4408922Swilliam.wang@arm.com return getInstPort(); 4418850Sandreas.hansson@arm.com else 4428922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4438850Sandreas.hansson@arm.com} 4448850Sandreas.hansson@arm.com 445180SN/Avoid 4462680Sktlim@umich.eduBaseCPU::registerThreadContexts() 447180SN/A{ 44811146Smitch.hayenga@arm.com assert(system->multiThread || numThreads == 1); 44911146Smitch.hayenga@arm.com 4506221Snate@binkert.org ThreadID size = threadContexts.size(); 4516221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4526221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4532378SN/A 45411146Smitch.hayenga@arm.com if (system->multiThread) { 45511146Smitch.hayenga@arm.com tc->setContextId(system->registerThreadContext(tc)); 45611146Smitch.hayenga@arm.com } else { 4575718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 45811146Smitch.hayenga@arm.com } 4598779Sgblack@eecs.umich.edu 4608779Sgblack@eecs.umich.edu if (!FullSystem) 4618779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 462180SN/A } 463180SN/A} 464180SN/A 465180SN/A 4664000Ssaidi@eecs.umich.eduint 4674000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 4684000Ssaidi@eecs.umich.edu{ 4696221Snate@binkert.org ThreadID size = threadContexts.size(); 4706221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4716221Snate@binkert.org if (tc == threadContexts[tid]) 4726221Snate@binkert.org return tid; 4734000Ssaidi@eecs.umich.edu } 4744000Ssaidi@eecs.umich.edu return 0; 4754000Ssaidi@eecs.umich.edu} 4764000Ssaidi@eecs.umich.edu 477180SN/Avoid 4782798Sktlim@umich.eduBaseCPU::switchOut() 479180SN/A{ 4809430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 4819430SAndreas.Sandberg@ARM.com _switchedOut = true; 4822359SN/A if (profileEvent && profileEvent->scheduled()) 4835606Snate@binkert.org deschedule(profileEvent); 4849446SAndreas.Sandberg@ARM.com 4859446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 4869446SAndreas.Sandberg@ARM.com // it gets switched in later. 4879446SAndreas.Sandberg@ARM.com flushTLBs(); 488180SN/A} 489180SN/A 490180SN/Avoid 4918737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 492180SN/A{ 4932680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 4949152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 4959430SAndreas.Sandberg@ARM.com assert(_switchedOut); 4969430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 4979332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 4989332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 4999430SAndreas.Sandberg@ARM.com _switchedOut = false; 5005712Shsul@eecs.umich.edu 5016221Snate@binkert.org ThreadID size = threadContexts.size(); 5026221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5032680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 5042680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 505180SN/A 5062680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 5072651Ssaidi@eecs.umich.edu 5082680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 5092651Ssaidi@eecs.umich.edu 5105714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 5115715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 5125714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 5132359SN/A 5145875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 5155875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 5165875Ssteve.reinhardt@amd.com * point. 5175875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 5185217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 5195875Ssteve.reinhardt@amd.com */ 5207781SAli.Saidi@ARM.com 5219294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 5229294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 5239294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 5249294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 5257781SAli.Saidi@ARM.com 5267781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 5279178Sandreas.hansson@arm.com if (new_itb_port) { 5289178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 5297781SAli.Saidi@ARM.com assert(old_itb_port); 5309178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 5319294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 5329178Sandreas.hansson@arm.com old_itb_port->unbind(); 5338922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 5347781SAli.Saidi@ARM.com } 5359178Sandreas.hansson@arm.com if (new_dtb_port) { 5369178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 5377781SAli.Saidi@ARM.com assert(old_dtb_port); 5389178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 5399294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 5409178Sandreas.hansson@arm.com old_dtb_port->unbind(); 5418922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 5427781SAli.Saidi@ARM.com } 54310194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 54410194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 5458733Sgeoffrey.blake@arm.com 5468887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 5478887Sgeoffrey.blake@arm.com // objects over in the switch 5488887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 5498887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 5508887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 5519294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 5528922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 5539294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 5548922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 5559294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 5568922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 5579294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 5588922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 5598733Sgeoffrey.blake@arm.com 56010194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 56110194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 56210194SGeoffrey.Blake@arm.com 5638887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 5649178Sandreas.hansson@arm.com if (new_checker_itb_port) { 5659178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 5668887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 5679178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 5689294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 5699294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 5709178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 5718922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 5728887Sgeoffrey.blake@arm.com } 5739178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 5749178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 5758887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 5769178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 5779294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 5789294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 5799178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 5808922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 5818887Sgeoffrey.blake@arm.com } 5828733Sgeoffrey.blake@arm.com } 583180SN/A } 584605SN/A 5853520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 58611150Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 58711150Smitch.hayenga@arm.com interrupts[tid]->setCPU(this); 58811150Smitch.hayenga@arm.com } 58911150Smitch.hayenga@arm.com oldCPU->interrupts.clear(); 5902254SN/A 5918779Sgblack@eecs.umich.edu if (FullSystem) { 5928779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 5938779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 5942254SN/A 5958779Sgblack@eecs.umich.edu if (profileEvent) 5968779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 5978779Sgblack@eecs.umich.edu } 5984192Sktlim@umich.edu 5999178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 6009178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 6019178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 6029178Sandreas.hansson@arm.com // we are switching to. 6039178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 6049178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 6059294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 6069178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 6079178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 6084192Sktlim@umich.edu 6099178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 6109178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 6119294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 6129178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 6139178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 614180SN/A} 615180SN/A 6169446SAndreas.Sandberg@ARM.comvoid 6179446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 6189446SAndreas.Sandberg@ARM.com{ 6199446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 6209446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 6219446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 6229446SAndreas.Sandberg@ARM.com 6239446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 6249446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 6259446SAndreas.Sandberg@ARM.com if (checker) { 6269446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 6279446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 6289446SAndreas.Sandberg@ARM.com } 6299446SAndreas.Sandberg@ARM.com } 6309446SAndreas.Sandberg@ARM.com} 6319446SAndreas.Sandberg@ARM.com 632180SN/A 6335536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 6345606Snate@binkert.org : cpu(_cpu), interval(_interval) 6351917SN/A{ } 6361917SN/A 6371917SN/Avoid 6381917SN/ABaseCPU::ProfileEvent::process() 6391917SN/A{ 6406221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 6416221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 6422680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 6432680Sktlim@umich.edu tc->profileSample(); 6441917SN/A } 6452254SN/A 6467823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 6471917SN/A} 6481917SN/A 6492SN/Avoid 65010905Sandreas.sandberg@arm.comBaseCPU::serialize(CheckpointOut &cp) const 651921SN/A{ 6524000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 6539332Sdam.sunwoo@arm.com 6549448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6559448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 6569448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 6579448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 6589448SAndreas.Sandberg@ARM.com * system. */ 6599448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 6609332Sdam.sunwoo@arm.com 6619448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 6629448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 66310905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 66411150Smitch.hayenga@arm.com interrupts[i]->serialize(cp); 66510905Sandreas.sandberg@arm.com serializeThread(cp, i); 6669448SAndreas.Sandberg@ARM.com } 6679448SAndreas.Sandberg@ARM.com } 668921SN/A} 669921SN/A 670921SN/Avoid 67110905Sandreas.sandberg@arm.comBaseCPU::unserialize(CheckpointIn &cp) 672921SN/A{ 6734000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 6749448SAndreas.Sandberg@ARM.com 6759448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6769448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 6779448SAndreas.Sandberg@ARM.com 6789448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 67910905Sandreas.sandberg@arm.com for (ThreadID i = 0; i < numThreads; ++i) { 68010905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 68111150Smitch.hayenga@arm.com interrupts[i]->unserialize(cp); 68210905Sandreas.sandberg@arm.com unserializeThread(cp, i); 68310905Sandreas.sandberg@arm.com } 6849448SAndreas.Sandberg@ARM.com } 685921SN/A} 686921SN/A 6871191SN/Avoid 6889749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 6899749Sandreas@sandberg.pp.se{ 6909749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 6919983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 6929749Sandreas@sandberg.pp.se 6939749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 6949749Sandreas@sandberg.pp.se} 6959749Sandreas@sandberg.pp.se 69610529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 69710529Smorr@cs.wisc.edu armed = false; 69810529Smorr@cs.wisc.edu waiting = false; 69910529Smorr@cs.wisc.edu gotWakeup = false; 70010529Smorr@cs.wisc.edu} 70110529Smorr@cs.wisc.edu 70210529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 70310529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 70411321Ssteve.reinhardt@amd.com if (armed && waiting) { 70511321Ssteve.reinhardt@amd.com if (pAddr == pkt->getAddr()) { 70610529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 70710529Smorr@cs.wisc.edu pkt->getAddr()); 70810529Smorr@cs.wisc.edu waiting = false; 70910529Smorr@cs.wisc.edu return true; 71010529Smorr@cs.wisc.edu } 71110529Smorr@cs.wisc.edu } 71210529Smorr@cs.wisc.edu return false; 71310529Smorr@cs.wisc.edu} 71410529Smorr@cs.wisc.edu 7159749Sandreas@sandberg.pp.sevoid 7169749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 7179749Sandreas@sandberg.pp.se{ 7189749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 7199983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7209749Sandreas@sandberg.pp.se 7219749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 7229749Sandreas@sandberg.pp.se} 7239749Sandreas@sandberg.pp.se 7249749Sandreas@sandberg.pp.se 7259749Sandreas@sandberg.pp.sevoid 7261191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 7271191SN/A{ 7281191SN/A if (!debugSymbolTable) 7291191SN/A return; 7301191SN/A 7311191SN/A // if pc enters different function, print new function symbol and 7321191SN/A // update saved range. Otherwise do nothing. 7331191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 7341191SN/A string sym_str; 7351191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 7361191SN/A currentFunctionStart, 7371191SN/A currentFunctionEnd); 7381191SN/A 7391191SN/A if (!found) { 7401191SN/A // no symbol found: use addr as label 7411191SN/A sym_str = csprintf("0x%x", pc); 7421191SN/A currentFunctionStart = pc; 7431191SN/A currentFunctionEnd = pc + 1; 7441191SN/A } 7451191SN/A 7461191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 7477823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 7487823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 7491191SN/A } 7501191SN/A} 751