base.cc revision 1098
1/* 2 * Copyright (c) 2002-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <string> 30#include <sstream> 31#include <iostream> 32 33#include "cpu/base_cpu.hh" 34#include "base/cprintf.hh" 35#include "cpu/exec_context.hh" 36#include "base/misc.hh" 37#include "sim/param.hh" 38#include "sim/sim_events.hh" 39 40using namespace std; 41 42vector<BaseCPU *> BaseCPU::cpuList; 43 44// This variable reflects the max number of threads in any CPU. Be 45// careful to only use it once all the CPUs that you care about have 46// been initialized 47int maxThreadsPerCPU = 1; 48 49#ifdef FULL_SYSTEM 50BaseCPU::BaseCPU(const string &_name, int _number_of_threads, 51 Counter max_insts_any_thread, 52 Counter max_insts_all_threads, 53 Counter max_loads_any_thread, 54 Counter max_loads_all_threads, 55 System *_system, Tick freq) 56 : SimObject(_name), frequency(freq), 57 number_of_threads(_number_of_threads), system(_system) 58#else 59BaseCPU::BaseCPU(const string &_name, int _number_of_threads, 60 Counter max_insts_any_thread, 61 Counter max_insts_all_threads, 62 Counter max_loads_any_thread, 63 Counter max_loads_all_threads) 64 : SimObject(_name), number_of_threads(_number_of_threads) 65#endif 66{ 67 // add self to global list of CPUs 68 cpuList.push_back(this); 69 70 if (number_of_threads > maxThreadsPerCPU) 71 maxThreadsPerCPU = number_of_threads; 72 73 // allocate per-thread instruction-based event queues 74 comInstEventQueue = new (EventQueue *)[number_of_threads]; 75 for (int i = 0; i < number_of_threads; ++i) 76 comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 77 78 // 79 // set up instruction-count-based termination events, if any 80 // 81 if (max_insts_any_thread != 0) 82 for (int i = 0; i < number_of_threads; ++i) 83 new SimExitEvent(comInstEventQueue[i], max_insts_any_thread, 84 "a thread reached the max instruction count"); 85 86 if (max_insts_all_threads != 0) { 87 // allocate & initialize shared downcounter: each event will 88 // decrement this when triggered; simulation will terminate 89 // when counter reaches 0 90 int *counter = new int; 91 *counter = number_of_threads; 92 for (int i = 0; i < number_of_threads; ++i) 93 new CountedExitEvent(comInstEventQueue[i], 94 "all threads reached the max instruction count", 95 max_insts_all_threads, *counter); 96 } 97 98 // allocate per-thread load-based event queues 99 comLoadEventQueue = new (EventQueue *)[number_of_threads]; 100 for (int i = 0; i < number_of_threads; ++i) 101 comLoadEventQueue[i] = new EventQueue("load-based event queue"); 102 103 // 104 // set up instruction-count-based termination events, if any 105 // 106 if (max_loads_any_thread != 0) 107 for (int i = 0; i < number_of_threads; ++i) 108 new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread, 109 "a thread reached the max load count"); 110 111 if (max_loads_all_threads != 0) { 112 // allocate & initialize shared downcounter: each event will 113 // decrement this when triggered; simulation will terminate 114 // when counter reaches 0 115 int *counter = new int; 116 *counter = number_of_threads; 117 for (int i = 0; i < number_of_threads; ++i) 118 new CountedExitEvent(comLoadEventQueue[i], 119 "all threads reached the max load count", 120 max_loads_all_threads, *counter); 121 } 122 123#ifdef FULL_SYSTEM 124 memset(interrupts, 0, sizeof(interrupts)); 125 intstatus = 0; 126#endif 127} 128 129 130void 131BaseCPU::regStats() 132{ 133 using namespace Stats; 134 135 numCycles 136 .name(name() + ".numCycles") 137 .desc("number of cpu cycles simulated") 138 ; 139 140 int size = execContexts.size(); 141 if (size > 1) { 142 for (int i = 0; i < size; ++i) { 143 stringstream namestr; 144 ccprintf(namestr, "%s.ctx%d", name(), i); 145 execContexts[i]->regStats(namestr.str()); 146 } 147 } else if (size == 1) 148 execContexts[0]->regStats(name()); 149} 150 151 152void 153BaseCPU::registerExecContexts() 154{ 155 for (int i = 0; i < execContexts.size(); ++i) { 156 ExecContext *xc = execContexts[i]; 157 int cpu_id; 158 159#ifdef FULL_SYSTEM 160 cpu_id = system->registerExecContext(xc); 161#else 162 cpu_id = xc->process->registerExecContext(xc); 163#endif 164 165 xc->cpu_id = cpu_id; 166 } 167} 168 169 170void 171BaseCPU::switchOut() 172{ 173 // default: do nothing 174} 175 176void 177BaseCPU::takeOverFrom(BaseCPU *oldCPU) 178{ 179 assert(execContexts.size() == oldCPU->execContexts.size()); 180 181 for (int i = 0; i < execContexts.size(); ++i) { 182 ExecContext *newXC = execContexts[i]; 183 ExecContext *oldXC = oldCPU->execContexts[i]; 184 185 newXC->takeOverFrom(oldXC); 186 assert(newXC->cpu_id == oldXC->cpu_id); 187#ifdef FULL_SYSTEM 188 system->replaceExecContext(newXC, newXC->cpu_id); 189#else 190 assert(newXC->process == oldXC->process); 191 newXC->process->replaceExecContext(newXC, newXC->cpu_id); 192#endif 193 } 194 195#ifdef FULL_SYSTEM 196 for (int i = 0; i < NumInterruptLevels; ++i) 197 interrupts[i] = oldCPU->interrupts[i]; 198 intstatus = oldCPU->intstatus; 199#endif 200} 201 202 203#ifdef FULL_SYSTEM 204void 205BaseCPU::post_interrupt(int int_num, int index) 206{ 207 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 208 209 if (int_num < 0 || int_num >= NumInterruptLevels) 210 panic("int_num out of bounds\n"); 211 212 if (index < 0 || index >= sizeof(uint64_t) * 8) 213 panic("int_num out of bounds\n"); 214 215 AlphaISA::check_interrupts = 1; 216 interrupts[int_num] |= 1 << index; 217 intstatus |= (ULL(1) << int_num); 218} 219 220void 221BaseCPU::clear_interrupt(int int_num, int index) 222{ 223 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 224 225 if (int_num < 0 || int_num >= NumInterruptLevels) 226 panic("int_num out of bounds\n"); 227 228 if (index < 0 || index >= sizeof(uint64_t) * 8) 229 panic("int_num out of bounds\n"); 230 231 interrupts[int_num] &= ~(1 << index); 232 if (interrupts[int_num] == 0) 233 intstatus &= ~(ULL(1) << int_num); 234} 235 236void 237BaseCPU::clear_interrupts() 238{ 239 DPRINTF(Interrupt, "Interrupts all cleared\n"); 240 241 memset(interrupts, 0, sizeof(interrupts)); 242 intstatus = 0; 243} 244 245 246void 247BaseCPU::serialize(std::ostream &os) 248{ 249 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 250 SERIALIZE_SCALAR(intstatus); 251} 252 253void 254BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 255{ 256 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 257 UNSERIALIZE_SCALAR(intstatus); 258} 259 260#endif // FULL_SYSTEM 261 262DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 263