activity.hh revision 9086
112276Sanouk.vanlaer@arm.com/*
28839Sandreas.hansson@arm.com * Copyright (c) 2006 The Regents of The University of Michigan
38839Sandreas.hansson@arm.com * All rights reserved.
48839Sandreas.hansson@arm.com *
58839Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without
68839Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are
78839Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright
88839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer;
98839Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright
108839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the
118839Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution;
128839Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its
135335Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
147897Shestness@cs.utexas.edu * this software without specific prior written permission.
154486Sbinkertn@umich.edu *
164486Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
174486Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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274486Sbinkertn@umich.edu *
284486Sbinkertn@umich.edu * Authors: Kevin Lim
294486Sbinkertn@umich.edu */
304486Sbinkertn@umich.edu
314486Sbinkertn@umich.edu#ifndef __CPU_ACTIVITY_HH__
324486Sbinkertn@umich.edu#define __CPU_ACTIVITY_HH__
334486Sbinkertn@umich.edu
344486Sbinkertn@umich.edu#include "base/trace.hh"
354486Sbinkertn@umich.edu#include "cpu/timebuf.hh"
364486Sbinkertn@umich.edu
374486Sbinkertn@umich.edu/**
384486Sbinkertn@umich.edu * ActivityRecorder helper class that informs the CPU if it can switch
394486Sbinkertn@umich.edu * over to being idle or not.  It works by having a time buffer as
404486Sbinkertn@umich.edu * long as any time buffer in the CPU, and the CPU and all of its
417897Shestness@cs.utexas.edu * stages inform the ActivityRecorder when they write to any time
428839Sandreas.hansson@arm.com * buffer.  The ActivityRecorder marks a 1 in the "0" slot of the time
434486Sbinkertn@umich.edu * buffer any time a stage writes to a time buffer, and it advances
446654Snate@binkert.org * its time buffer at the same time as all other stages.  The
456654Snate@binkert.org * ActivityRecorder also records if a stage has activity to do next
4611988Sandreas.sandberg@arm.com * cycle.  The recorder keeps a count of these two.  Thus any time the
476654Snate@binkert.org * count is non-zero, there is either communication still in flight,
483102SN/A * or activity that still must be done, meaning that the CPU can not
493102SN/A * idle.  If count is zero, then the CPU can safely idle as it has no
506654Snate@binkert.org * more outstanding work to do.
5110720Sandreas.hansson@arm.com */
524776Sgblack@eecs.umich.educlass ActivityRecorder
5310663SAli.Saidi@ARM.com{
546654Snate@binkert.org  public:
559793Sakash.bagdia@arm.com    ActivityRecorder(const std::string &name, int num_stages,
562667SN/A                     int longest_latency, int count);
574776Sgblack@eecs.umich.edu    ~ActivityRecorder();
584776Sgblack@eecs.umich.edu
596654Snate@binkert.org    /** Records that there is activity this cycle. */
606023Snate@binkert.org    void activity();
618745Sgblack@eecs.umich.edu
629384SAndreas.Sandberg@arm.com    /** Advances the activity buffer, decrementing the activityCount
639384SAndreas.Sandberg@arm.com     *  if active communication just left the time buffer, and
646654Snate@binkert.org     *  determining if there is no activity.
656022Sgblack@eecs.umich.edu     */
668745Sgblack@eecs.umich.edu    void advance();
679384SAndreas.Sandberg@arm.com
689384SAndreas.Sandberg@arm.com    /** Marks a stage as active. */
696654Snate@binkert.org    void activateStage(const int idx);
706022Sgblack@eecs.umich.edu
718745Sgblack@eecs.umich.edu    /** Deactivates a stage. */
729384SAndreas.Sandberg@arm.com    void deactivateStage(const int idx);
739384SAndreas.Sandberg@arm.com
746654Snate@binkert.org    /** Returns how many things are active within the recorder. */
756022Sgblack@eecs.umich.edu    int getActivityCount() { return activityCount; }
768745Sgblack@eecs.umich.edu
779384SAndreas.Sandberg@arm.com    /** Sets the count to a starting value.  Can be used to disable
789384SAndreas.Sandberg@arm.com     * the idling option.
796654Snate@binkert.org     */
8010037SARM gem5 Developers    void setActivityCount(int count)
818745Sgblack@eecs.umich.edu    { activityCount = count; }
829384SAndreas.Sandberg@arm.com
839384SAndreas.Sandberg@arm.com    /** Returns if the CPU should be active. */
846691Stjones1@inf.ed.ac.uk    bool active() { return activityCount; }
856691Stjones1@inf.ed.ac.uk
868745Sgblack@eecs.umich.edu    /** Clears the time buffer and the activity count. */
879384SAndreas.Sandberg@arm.com    void reset();
889384SAndreas.Sandberg@arm.com
8911723Sar4jc@virginia.edu    /** Debug function to dump the contents of the time buffer. */
9011723Sar4jc@virginia.edu    void dump();
9111723Sar4jc@virginia.edu
9211723Sar4jc@virginia.edu    /** Debug function to ensure that the activity count matches the
9311723Sar4jc@virginia.edu     * contents of the time buffer.
944486Sbinkertn@umich.edu     */
955529Snate@binkert.org    void validate();
961366SN/A
971310SN/A  private:
989338SAndreas.Sandberg@arm.com    // provide name() for DPRINTF.
999254SAndreas.Sandberg@arm.com    std::string _name;
10011988Sandreas.sandberg@arm.com    const std::string &name() { return _name; }
10111988Sandreas.sandberg@arm.com
10211988Sandreas.sandberg@arm.com    /** Time buffer that tracks if any cycles has active communication
10311988Sandreas.sandberg@arm.com     *  in them.  It should be as long as the longest communication
10411988Sandreas.sandberg@arm.com     *  latency in the system.  Each time any time buffer is written,
10511988Sandreas.sandberg@arm.com     *  the activity buffer should also be written to. The
10611988Sandreas.sandberg@arm.com     *  activityBuffer is advanced along with all the other time
10711988Sandreas.sandberg@arm.com     *  buffers, so it should have a 1 somewhere in it only if there
10811988Sandreas.sandberg@arm.com     *  is active communication in a time buffer.
10911988Sandreas.sandberg@arm.com     */
1109254SAndreas.Sandberg@arm.com    TimeBuffer<bool> activityBuffer;
1119518SAndreas.Sandberg@ARM.com
1129518SAndreas.Sandberg@ARM.com    /** Longest latency time buffer in the CPU. */
1139518SAndreas.Sandberg@ARM.com    int longestLatency;
1149518SAndreas.Sandberg@ARM.com
1159518SAndreas.Sandberg@ARM.com    /** Tracks how many stages and cycles of time buffer have
1169518SAndreas.Sandberg@ARM.com     *  activity. Stages increment this count when they switch to
1179518SAndreas.Sandberg@ARM.com     *  active, and decrement it when they switch to
1189518SAndreas.Sandberg@ARM.com     *  inactive. Whenever a cycle that previously had no information
1199518SAndreas.Sandberg@ARM.com     *  is written in the time buffer, this is incremented. When a
1209518SAndreas.Sandberg@ARM.com     *  cycle that had information exits the time buffer due to age,
1219518SAndreas.Sandberg@ARM.com     *  this count is decremented. When the count is 0, there is no
1229518SAndreas.Sandberg@ARM.com     *  activity in the CPU, and it can be descheduled.
1239518SAndreas.Sandberg@ARM.com     */
1249518SAndreas.Sandberg@ARM.com    int activityCount;
1259518SAndreas.Sandberg@ARM.com
1269518SAndreas.Sandberg@ARM.com    /** Number of stages that can be marked as active or inactive. */
1279518SAndreas.Sandberg@ARM.com    int numStages;
1289518SAndreas.Sandberg@ARM.com
1299518SAndreas.Sandberg@ARM.com    /** Records which stages are active/inactive. */
1309254SAndreas.Sandberg@arm.com    bool *stageActive;
1319254SAndreas.Sandberg@arm.com};
1329254SAndreas.Sandberg@arm.com
1339254SAndreas.Sandberg@arm.com#endif // __CPU_ACTIVITY_HH__
1342901SN/A