activity.hh revision 2348
11689SN/A/*
27854SAli.Saidi@ARM.com * Copyright (c) 2006 The Regents of The University of Michigan
37854SAli.Saidi@ARM.com * All rights reserved.
47854SAli.Saidi@ARM.com *
57854SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
67854SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
77854SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
87854SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
97854SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
107854SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
117854SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
127854SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
137854SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
142329SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
271689SN/A */
281689SN/A
291689SN/A#ifndef __CPU_ACTIVITY_HH__
301689SN/A#define __CPU_ACTIVITY_HH__
311689SN/A
321689SN/A#include "base/timebuf.hh"
331689SN/A#include "base/trace.hh"
341689SN/A
351689SN/A/**
361689SN/A * ActivityRecorder helper class that informs the CPU if it can switch
371689SN/A * over to being idle or not.  It works by having a time buffer as
381689SN/A * long as any time buffer in the CPU, and the CPU and all of its
392665Ssaidi@eecs.umich.edu * stages inform the ActivityRecorder when they write to any time
402665Ssaidi@eecs.umich.edu * buffer.  The ActivityRecorder marks a 1 in the "0" slot of the time
412935Sksewell@umich.edu * buffer any time a stage writes to a time buffer, and it advances
421689SN/A * its time buffer at the same time as all other stages.  The
431689SN/A * ActivityRecorder also records if a stage has activity to do next
441060SN/A * cycle.  The recorder keeps a count of these two.  Thus any time the
451060SN/A * count is non-zero, there is either communication still in flight,
463773Sgblack@eecs.umich.edu * or activity that still must be done, meaning that the CPU can not
476329Sgblack@eecs.umich.edu * idle.  If count is zero, then the CPU can safely idle as it has no
481858SN/A * more outstanding work to do.
496658Snate@binkert.org */
501717SN/Aclass ActivityRecorder {
518232Snate@binkert.org  public:
528232Snate@binkert.org    ActivityRecorder(int num_stages, int longest_latency, int count);
535529Snate@binkert.org
541060SN/A    /** Records that there is activity this cycle. */
556221Snate@binkert.org    void activity();
566221Snate@binkert.org
571061SN/A    /** Advances the activity buffer, decrementing the activityCount
585529Snate@binkert.org     *  if active communication just left the time buffer, and
594329Sktlim@umich.edu     *  determining if there is no activity.
604329Sktlim@umich.edu     */
612292SN/A    void advance();
622292SN/A
632292SN/A    /** Marks a stage as active. */
642292SN/A    void activateStage(const int idx);
653788Sgblack@eecs.umich.edu
663798Sgblack@eecs.umich.edu    /** Deactivates a stage. */
675529Snate@binkert.org    void deactivateStage(const int idx);
682361SN/A
691060SN/A    /** Returns how many things are active within the recorder. */
702292SN/A    int getActivityCount() { return activityCount; }
712292SN/A
726221Snate@binkert.org    /** Sets the count to a starting value.  Can be used to disable
736221Snate@binkert.org     * the idling option.
742292SN/A     */
756221Snate@binkert.org    void setActivityCount(int count)
766221Snate@binkert.org    { activityCount = count; }
776221Snate@binkert.org
782292SN/A    /** Returns if the CPU should be active. */
796221Snate@binkert.org    bool active() { return activityCount; }
806221Snate@binkert.org
816221Snate@binkert.org    /** Clears the time buffer and the activity count. */
822292SN/A    void reset();
836221Snate@binkert.org
842292SN/A    /** Debug function to dump the contents of the time buffer. */
856221Snate@binkert.org    void dump();
862292SN/A
876221Snate@binkert.org    /** Debug function to ensure that the activity count matches the
882292SN/A     * contents of the time buffer.
892292SN/A     */
902292SN/A    void validate();
912292SN/A
922292SN/A  private:
932292SN/A    /** Time buffer that tracks if any cycles has active communication
942292SN/A     *  in them.  It should be as long as the longest communication
952292SN/A     *  latency in the system.  Each time any time buffer is written,
962292SN/A     *  the activity buffer should also be written to. The
972292SN/A     *  activityBuffer is advanced along with all the other time
982292SN/A     *  buffers, so it should have a 1 somewhere in it only if there
991060SN/A     *  is active communication in a time buffer.
1001060SN/A     */
1011061SN/A    TimeBuffer<bool> activityBuffer;
1021060SN/A
1032292SN/A    /** Longest latency time buffer in the CPU. */
1041062SN/A    int longestLatency;
1051062SN/A
1062301SN/A    /** Tracks how many stages and cycles of time buffer have
1071062SN/A     *  activity. Stages increment this count when they switch to
1081062SN/A     *  active, and decrement it when they switch to
1091062SN/A     *  inactive. Whenever a cycle that previously had no information
1102301SN/A     *  is written in the time buffer, this is incremented. When a
1111062SN/A     *  cycle that had information exits the time buffer due to age,
1121062SN/A     *  this count is decremented. When the count is 0, there is no
1131062SN/A     *  activity in the CPU, and it can be descheduled.
1142301SN/A     */
1151062SN/A    int activityCount;
1161062SN/A
1172301SN/A    /** Number of stages that can be marked as active or inactive. */
1182301SN/A    int numStages;
1192301SN/A
1202301SN/A    /** Records which stages are active/inactive. */
1212292SN/A    bool *stageActive;
1222301SN/A};
1232292SN/A
1242292SN/A#endif // __CPU_ACTIVITY_HH__
1251062SN/A