activity.cc revision 8232
12348SN/A/*
22348SN/A * Copyright (c) 2006 The Regents of The University of Michigan
32348SN/A * All rights reserved.
42348SN/A *
52348SN/A * Redistribution and use in source and binary forms, with or without
62348SN/A * modification, are permitted provided that the following conditions are
72348SN/A * met: redistributions of source code must retain the above copyright
82348SN/A * notice, this list of conditions and the following disclaimer;
92348SN/A * redistributions in binary form must reproduce the above copyright
102348SN/A * notice, this list of conditions and the following disclaimer in the
112348SN/A * documentation and/or other materials provided with the distribution;
122348SN/A * neither the name of the copyright holders nor the names of its
132348SN/A * contributors may be used to endorse or promote products derived from
142348SN/A * this software without specific prior written permission.
152348SN/A *
162348SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172348SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182348SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192348SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202348SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212348SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222348SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232348SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242348SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252348SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262348SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272689Sktlim@umich.edu *
282689Sktlim@umich.edu * Authors: Kevin Lim
292348SN/A */
302325SN/A
315804Snate@binkert.org#include <string>
323918Ssaidi@eecs.umich.edu
338229Snate@binkert.org#include "cpu/activity.hh"
347813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh"
358232Snate@binkert.org#include "debug/Activity.hh"
362325SN/A
375804Snate@binkert.orgusing namespace std;
385804Snate@binkert.org
395804Snate@binkert.orgActivityRecorder::ActivityRecorder(const string &name, int num_stages,
405804Snate@binkert.org    int longest_latency, int activity)
415804Snate@binkert.org    : _name(name), activityBuffer(longest_latency, 0),
425804Snate@binkert.org      longestLatency(longest_latency), activityCount(activity),
435804Snate@binkert.org      numStages(num_stages)
442325SN/A{
452325SN/A    stageActive = new bool[numStages];
463918Ssaidi@eecs.umich.edu    std::memset(stageActive, 0, numStages);
472325SN/A}
482325SN/A
492325SN/Avoid
502325SN/AActivityRecorder::activity()
512325SN/A{
522348SN/A    // If we've already recorded activity for this cycle, we don't
532348SN/A    // want to increment the count any more.
542325SN/A    if (activityBuffer[0]) {
552325SN/A        return;
562325SN/A    }
572325SN/A
582325SN/A    activityBuffer[0] = true;
592325SN/A
602325SN/A    ++activityCount;
612325SN/A
622325SN/A    DPRINTF(Activity, "Activity: %i\n", activityCount);
632325SN/A}
642325SN/A
652325SN/Avoid
662325SN/AActivityRecorder::advance()
672325SN/A{
682348SN/A    // If there's a 1 in the slot that is about to be erased once the
692348SN/A    // time buffer advances, then decrement the activityCount.
702325SN/A    if (activityBuffer[-longestLatency]) {
712325SN/A        --activityCount;
722325SN/A
732325SN/A        assert(activityCount >= 0);
742325SN/A
752325SN/A        DPRINTF(Activity, "Activity: %i\n", activityCount);
762325SN/A
772325SN/A        if (activityCount == 0) {
782325SN/A            DPRINTF(Activity, "No activity left!\n");
792325SN/A        }
802325SN/A    }
812325SN/A
822325SN/A    activityBuffer.advance();
832325SN/A}
842325SN/A
852325SN/Avoid
862325SN/AActivityRecorder::activateStage(const int idx)
872325SN/A{
882348SN/A    // Increment the activity count if this stage wasn't already active.
892325SN/A    if (!stageActive[idx]) {
902325SN/A        ++activityCount;
912325SN/A
922325SN/A        stageActive[idx] = true;
932325SN/A
942325SN/A        DPRINTF(Activity, "Activity: %i\n", activityCount);
952325SN/A    } else {
962325SN/A        DPRINTF(Activity, "Stage %i already active.\n", idx);
972325SN/A    }
982325SN/A
992325SN/A//    assert(activityCount < longestLatency + numStages + 1);
1002325SN/A}
1012325SN/A
1022325SN/Avoid
1032325SN/AActivityRecorder::deactivateStage(const int idx)
1042325SN/A{
1052348SN/A    // Decrement the activity count if this stage was active.
1062325SN/A    if (stageActive[idx]) {
1072325SN/A        --activityCount;
1082325SN/A
1092325SN/A        stageActive[idx] = false;
1102325SN/A
1112325SN/A        DPRINTF(Activity, "Activity: %i\n", activityCount);
1122325SN/A    } else {
1132325SN/A        DPRINTF(Activity, "Stage %i already inactive.\n", idx);
1142325SN/A    }
1152325SN/A
1162325SN/A    assert(activityCount >= 0);
1172325SN/A}
1182325SN/A
1192325SN/Avoid
1202325SN/AActivityRecorder::reset()
1212325SN/A{
1222325SN/A    activityCount = 0;
1233918Ssaidi@eecs.umich.edu    std::memset(stageActive, 0, numStages);
1242325SN/A    for (int i = 0; i < longestLatency + 1; ++i)
1252325SN/A        activityBuffer.advance();
1262325SN/A}
1272325SN/A
1282325SN/Avoid
1292325SN/AActivityRecorder::dump()
1302325SN/A{
1312325SN/A    for (int i = 0; i <= longestLatency; ++i) {
1322325SN/A        cprintf("[Idx:%i %i] ", i, activityBuffer[-i]);
1332325SN/A    }
1342325SN/A
1352325SN/A    cprintf("\n");
1362325SN/A
1372325SN/A    for (int i = 0; i < numStages; ++i) {
1382325SN/A        cprintf("[Stage:%i %i]\n", i, stageActive[i]);
1392325SN/A    }
1402325SN/A
1412325SN/A    cprintf("\n");
1422325SN/A
1432325SN/A    cprintf("Activity count: %i\n", activityCount);
1442325SN/A}
1452325SN/A
1462325SN/Avoid
1472325SN/AActivityRecorder::validate()
1482325SN/A{
1492325SN/A    int count = 0;
1502325SN/A    for (int i = 0; i <= longestLatency; ++i) {
1512325SN/A        if (activityBuffer[-i]) {
1522325SN/A            count++;
1532325SN/A        }
1542325SN/A    }
1552325SN/A
1562325SN/A    for (int i = 0; i < numStages; ++i) {
1572325SN/A        if (stageActive[i]) {
1582325SN/A            count++;
1592325SN/A        }
1602325SN/A    }
1612325SN/A
1622325SN/A    assert(count == activityCount);
1632325SN/A}
164