12348SN/A/* 22348SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32348SN/A * All rights reserved. 42348SN/A * 52348SN/A * Redistribution and use in source and binary forms, with or without 62348SN/A * modification, are permitted provided that the following conditions are 72348SN/A * met: redistributions of source code must retain the above copyright 82348SN/A * notice, this list of conditions and the following disclaimer; 92348SN/A * redistributions in binary form must reproduce the above copyright 102348SN/A * notice, this list of conditions and the following disclaimer in the 112348SN/A * documentation and/or other materials provided with the distribution; 122348SN/A * neither the name of the copyright holders nor the names of its 132348SN/A * contributors may be used to endorse or promote products derived from 142348SN/A * this software without specific prior written permission. 152348SN/A * 162348SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172348SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182348SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192348SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202348SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212348SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222348SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232348SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242348SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252348SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262348SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292348SN/A */ 302325SN/A 3111793Sbrandon.potter@amd.com#include "cpu/activity.hh" 3211793Sbrandon.potter@amd.com 335804Snate@binkert.org#include <string> 343918Ssaidi@eecs.umich.edu 357813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 368232Snate@binkert.org#include "debug/Activity.hh" 372325SN/A 385804Snate@binkert.orgusing namespace std; 395804Snate@binkert.org 405804Snate@binkert.orgActivityRecorder::ActivityRecorder(const string &name, int num_stages, 415804Snate@binkert.org int longest_latency, int activity) 425804Snate@binkert.org : _name(name), activityBuffer(longest_latency, 0), 435804Snate@binkert.org longestLatency(longest_latency), activityCount(activity), 445804Snate@binkert.org numStages(num_stages) 452325SN/A{ 462325SN/A stageActive = new bool[numStages]; 473918Ssaidi@eecs.umich.edu std::memset(stageActive, 0, numStages); 482325SN/A} 492325SN/A 509086Sandreas.hansson@arm.comActivityRecorder::~ActivityRecorder() 519086Sandreas.hansson@arm.com{ 529086Sandreas.hansson@arm.com delete[] stageActive; 539086Sandreas.hansson@arm.com} 549086Sandreas.hansson@arm.com 552325SN/Avoid 562325SN/AActivityRecorder::activity() 572325SN/A{ 582348SN/A // If we've already recorded activity for this cycle, we don't 592348SN/A // want to increment the count any more. 602325SN/A if (activityBuffer[0]) { 612325SN/A return; 622325SN/A } 632325SN/A 642325SN/A activityBuffer[0] = true; 652325SN/A 662325SN/A ++activityCount; 672325SN/A 682325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 692325SN/A} 702325SN/A 712325SN/Avoid 722325SN/AActivityRecorder::advance() 732325SN/A{ 742348SN/A // If there's a 1 in the slot that is about to be erased once the 752348SN/A // time buffer advances, then decrement the activityCount. 762325SN/A if (activityBuffer[-longestLatency]) { 772325SN/A --activityCount; 782325SN/A 792325SN/A assert(activityCount >= 0); 802325SN/A 812325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 822325SN/A 832325SN/A if (activityCount == 0) { 842325SN/A DPRINTF(Activity, "No activity left!\n"); 852325SN/A } 862325SN/A } 872325SN/A 882325SN/A activityBuffer.advance(); 892325SN/A} 902325SN/A 912325SN/Avoid 922325SN/AActivityRecorder::activateStage(const int idx) 932325SN/A{ 942348SN/A // Increment the activity count if this stage wasn't already active. 952325SN/A if (!stageActive[idx]) { 962325SN/A ++activityCount; 972325SN/A 982325SN/A stageActive[idx] = true; 992325SN/A 1002325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 1012325SN/A } else { 1022325SN/A DPRINTF(Activity, "Stage %i already active.\n", idx); 1032325SN/A } 1042325SN/A 1052325SN/A// assert(activityCount < longestLatency + numStages + 1); 1062325SN/A} 1072325SN/A 1082325SN/Avoid 1092325SN/AActivityRecorder::deactivateStage(const int idx) 1102325SN/A{ 1112348SN/A // Decrement the activity count if this stage was active. 1122325SN/A if (stageActive[idx]) { 1132325SN/A --activityCount; 1142325SN/A 1152325SN/A stageActive[idx] = false; 1162325SN/A 1172325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 1182325SN/A } else { 1192325SN/A DPRINTF(Activity, "Stage %i already inactive.\n", idx); 1202325SN/A } 1212325SN/A 1222325SN/A assert(activityCount >= 0); 1232325SN/A} 1242325SN/A 1252325SN/Avoid 1262325SN/AActivityRecorder::reset() 1272325SN/A{ 1282325SN/A activityCount = 0; 1293918Ssaidi@eecs.umich.edu std::memset(stageActive, 0, numStages); 1302325SN/A for (int i = 0; i < longestLatency + 1; ++i) 1312325SN/A activityBuffer.advance(); 1322325SN/A} 1332325SN/A 1342325SN/Avoid 1352325SN/AActivityRecorder::dump() 1362325SN/A{ 1372325SN/A for (int i = 0; i <= longestLatency; ++i) { 1382325SN/A cprintf("[Idx:%i %i] ", i, activityBuffer[-i]); 1392325SN/A } 1402325SN/A 1412325SN/A cprintf("\n"); 1422325SN/A 1432325SN/A for (int i = 0; i < numStages; ++i) { 1442325SN/A cprintf("[Stage:%i %i]\n", i, stageActive[i]); 1452325SN/A } 1462325SN/A 1472325SN/A cprintf("\n"); 1482325SN/A 1492325SN/A cprintf("Activity count: %i\n", activityCount); 1502325SN/A} 1512325SN/A 1522325SN/Avoid 1532325SN/AActivityRecorder::validate() 1542325SN/A{ 1552325SN/A int count = 0; 1562325SN/A for (int i = 0; i <= longestLatency; ++i) { 1572325SN/A if (activityBuffer[-i]) { 1582325SN/A count++; 1592325SN/A } 1602325SN/A } 1612325SN/A 1622325SN/A for (int i = 0; i < numStages; ++i) { 1632325SN/A if (stageActive[i]) { 1642325SN/A count++; 1652325SN/A } 1662325SN/A } 1672325SN/A 1682325SN/A assert(count == activityCount); 1692325SN/A} 170