StaticInstFlags.py revision 12768:9a299ec956ac
11689SN/A# Copyright (c) 2003-2005 The Regents of The University of Michigan 28707Sandreas.hansson@arm.com# Copyright (c) 2013 Advanced Micro Devices, Inc. 38707Sandreas.hansson@arm.com# All rights reserved. 48707Sandreas.hansson@arm.com# 58707Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 68707Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 78707Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 88707Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 98707Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 108707Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 118707Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 128707Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 138707Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 141689SN/A# this software without specific prior written permission. 157897Shestness@cs.utexas.edu# 161689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A# 281689SN/A# Authors: Steve Reinhardt 291689SN/A 301689SN/Afrom m5.params import * 311689SN/A 321689SN/A# Set of boolean static instruction properties. 331689SN/A# 341689SN/A# Notes: 351689SN/A# - The IsInteger and IsFloating flags are based on the class of registers 361689SN/A# accessed by the instruction. Although most instructions will have exactly 371689SN/A# one of these two flags set, it is possible for an instruction to have 381689SN/A# neither (e.g., direct unconditional branches, memory barriers) or both 391689SN/A# (e.g., an FP/int conversion). 402665Ssaidi@eecs.umich.edu# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set. 412665Ssaidi@eecs.umich.edu# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect 422756Sksewell@umich.edu# Control will be set, and exactly one of IsCondControl or IsUncondControl 437897Shestness@cs.utexas.edu# will be set. 441689SN/A# - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags 451689SN/A# since in the current model there's no other way for instructions to inject 462325SN/A# behavior into the pipeline outside of fetch. Once we go to an exec-in-exec 472325SN/A# CPU model we should be able to get rid of these flags and implement this 481060SN/A# behavior via the execute() methods. 491060SN/A 501060SN/Aclass StaticInstFlags(Enum): 512292SN/A wrapper_name = 'StaticInstFlags' 522292SN/A wrapper_is_struct = True 531681SN/A enum_name = 'Flags' 541060SN/A 552980Sgblack@eecs.umich.edu vals = [ 561060SN/A 'IsNop', # Is a no-op (no effect at all). 571858SN/A 586658Snate@binkert.org 'IsInteger', # References integer regs. 594598Sbinkertn@umich.edu 'IsFloating', # References FP regs. 601717SN/A 'IsCC', # References CC regs. 611717SN/A 'IsVector', # References Vector regs. 622292SN/A 'IsVectorElem', # References Vector reg elems. 632292SN/A 648229Snate@binkert.org 'IsMemRef', # References memory (load, store, or prefetch) 658229Snate@binkert.org 'IsLoad', # Reads from memory (load or prefetch). 668229Snate@binkert.org 'IsStore', # Writes to memory. 678229Snate@binkert.org 'IsAtomic', # Does atomic RMW to memory. 682817Sksewell@umich.edu 'IsStoreConditional', # Store conditional instruction. 698229Snate@binkert.org 'IsIndexed', # Accesses memory with an indexed address 701060SN/A # computation 711060SN/A 'IsInstPrefetch', # Instruction-cache prefetch. 722316SN/A 'IsDataPrefetch', # Data-cache prefetch. 732316SN/A 742680Sktlim@umich.edu 'IsControl', # Control transfer instruction. 752817Sksewell@umich.edu 'IsDirectControl', # PC relative control transfer. 762817Sksewell@umich.edu 'IsIndirectControl',# Register indirect control transfer. 772843Sktlim@umich.edu 'IsCondControl', # Conditional control transfer. 782843Sktlim@umich.edu 'IsUncondControl', # Unconditional control transfer. 792669Sktlim@umich.edu 'IsCall', # Subroutine call. 801060SN/A 'IsReturn', # Subroutine return. 811060SN/A 825529Snate@binkert.org 'IsCondDelaySlot', # Conditional Delay-Slot Instruction 835529Snate@binkert.org 842733Sktlim@umich.edu 'IsThreadSync', # Thread synchronization operation. 851060SN/A 861060SN/A 'IsSerializing', # Serializes pipeline: won't execute until all 871060SN/A # older instructions have committed. 885529Snate@binkert.org 'IsSerializeBefore', 892292SN/A 'IsSerializeAfter', 902292SN/A 'IsMemBarrier', # Is a memory barrier 911060SN/A 'IsWriteBarrier', # Is a write barrier 921060SN/A 'IsReadBarrier', # Is a read barrier 932348SN/A 'IsERET', # <- Causes the IFU to stall (MIPS ISA) 942348SN/A 952348SN/A 'IsNonSpeculative', # Should not be executed speculatively 962348SN/A 'IsQuiesce', # Is a quiesce instruction 972348SN/A 981060SN/A 'IsIprAccess', # Accesses IPRs 992733Sktlim@umich.edu 'IsUnverifiable', # Can't be verified by a checker 1001060SN/A 1011060SN/A 'IsSyscall', # Causes a system call to be emulated in syscall 1022325SN/A # emulation mode. 1031060SN/A 1041061SN/A # Flags for microcode 1054329Sktlim@umich.edu 'IsMacroop', # Is a macroop containing microops 1061060SN/A 'IsMicroop', # Is a microop 1075595Sgblack@eecs.umich.edu 'IsDelayedCommit', # This microop doesn't commit right away 1082292SN/A 'IsLastMicroop', # This microop ends a microop sequence 1092292SN/A 'IsFirstMicroop', # This microop begins a microop sequence 1102292SN/A # This flag doesn't do anything yet 1112292SN/A 'IsMicroBranch', # This microop branches within the microcode for 1122817Sksewell@umich.edu # a macroop 1132829Sksewell@umich.edu 'IsDspOp', 1141060SN/A 'IsSquashAfter' # Squash all uncommitted state after executed 1151060SN/A ] 1161060SN/A