StaticInstFlags.py revision 12110
110201SAndrew.Bardsley@arm.com# Copyright (c) 2003-2005 The Regents of The University of Michigan 210201SAndrew.Bardsley@arm.com# Copyright (c) 2013 Advanced Micro Devices, Inc. 310201SAndrew.Bardsley@arm.com# All rights reserved. 410201SAndrew.Bardsley@arm.com# 510201SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 610201SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 710201SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 810201SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 910201SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 1010201SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 1110201SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 1210201SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 1310201SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 1410201SAndrew.Bardsley@arm.com# this software without specific prior written permission. 1510201SAndrew.Bardsley@arm.com# 1610201SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710201SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810201SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910201SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010201SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110201SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210201SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310201SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410201SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510201SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610201SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710201SAndrew.Bardsley@arm.com# 2810201SAndrew.Bardsley@arm.com# Authors: Steve Reinhardt 2910201SAndrew.Bardsley@arm.com 3010201SAndrew.Bardsley@arm.comfrom m5.params import * 3110201SAndrew.Bardsley@arm.com 3210201SAndrew.Bardsley@arm.com# Set of boolean static instruction properties. 3310201SAndrew.Bardsley@arm.com# 3410201SAndrew.Bardsley@arm.com# Notes: 3510201SAndrew.Bardsley@arm.com# - The IsInteger and IsFloating flags are based on the class of registers 3610201SAndrew.Bardsley@arm.com# accessed by the instruction. Although most instructions will have exactly 3710201SAndrew.Bardsley@arm.com# one of these two flags set, it is possible for an instruction to have 3810201SAndrew.Bardsley@arm.com# neither (e.g., direct unconditional branches, memory barriers) or both 3910201SAndrew.Bardsley@arm.com# (e.g., an FP/int conversion). 4010201SAndrew.Bardsley@arm.com# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set. 4110201SAndrew.Bardsley@arm.com# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect 4210201SAndrew.Bardsley@arm.com# Control will be set, and exactly one of IsCondControl or IsUncondControl 4310201SAndrew.Bardsley@arm.com# will be set. 4410201SAndrew.Bardsley@arm.com# - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags 4510201SAndrew.Bardsley@arm.com# since in the current model there's no other way for instructions to inject 4610201SAndrew.Bardsley@arm.com# behavior into the pipeline outside of fetch. Once we go to an exec-in-exec 4710201SAndrew.Bardsley@arm.com# CPU model we should be able to get rid of these flags and implement this 4810201SAndrew.Bardsley@arm.com# behavior via the execute() methods. 4910201SAndrew.Bardsley@arm.com 5010201SAndrew.Bardsley@arm.comclass StaticInstFlags(Enum): 5110201SAndrew.Bardsley@arm.com wrapper_name = 'StaticInstFlags' 5210201SAndrew.Bardsley@arm.com wrapper_is_struct = True 5310201SAndrew.Bardsley@arm.com enum_name = 'Flags' 5410201SAndrew.Bardsley@arm.com 5510201SAndrew.Bardsley@arm.com vals = [ 5610201SAndrew.Bardsley@arm.com 'IsNop', # Is a no-op (no effect at all). 5710201SAndrew.Bardsley@arm.com 5810935Snilay@cs.wisc.edu 'IsInteger', # References integer regs. 5910935Snilay@cs.wisc.edu 'IsFloating', # References FP regs. 6010201SAndrew.Bardsley@arm.com 'IsCC', # References CC regs. 6112110SRekai.GonzalezAlberquilla@arm.com 'IsVector', # References Vector regs. 6212110SRekai.GonzalezAlberquilla@arm.com 'IsVectorElem', # References Vector reg elems. 6310201SAndrew.Bardsley@arm.com 6410201SAndrew.Bardsley@arm.com 'IsMemRef', # References memory (load, store, or prefetch) 6510201SAndrew.Bardsley@arm.com 'IsLoad', # Reads from memory (load or prefetch). 6610201SAndrew.Bardsley@arm.com 'IsStore', # Writes to memory. 6710201SAndrew.Bardsley@arm.com 'IsStoreConditional', # Store conditional instruction. 6810201SAndrew.Bardsley@arm.com 'IsIndexed', # Accesses memory with an indexed address 6910201SAndrew.Bardsley@arm.com # computation 7010201SAndrew.Bardsley@arm.com 'IsInstPrefetch', # Instruction-cache prefetch. 7110201SAndrew.Bardsley@arm.com 'IsDataPrefetch', # Data-cache prefetch. 7210201SAndrew.Bardsley@arm.com 7310201SAndrew.Bardsley@arm.com 'IsControl', # Control transfer instruction. 7410201SAndrew.Bardsley@arm.com 'IsDirectControl', # PC relative control transfer. 7510201SAndrew.Bardsley@arm.com 'IsIndirectControl',# Register indirect control transfer. 7610201SAndrew.Bardsley@arm.com 'IsCondControl', # Conditional control transfer. 7710201SAndrew.Bardsley@arm.com 'IsUncondControl', # Unconditional control transfer. 7810201SAndrew.Bardsley@arm.com 'IsCall', # Subroutine call. 7910201SAndrew.Bardsley@arm.com 'IsReturn', # Subroutine return. 8010201SAndrew.Bardsley@arm.com 8110201SAndrew.Bardsley@arm.com 'IsCondDelaySlot', # Conditional Delay-Slot Instruction 8210201SAndrew.Bardsley@arm.com 8310201SAndrew.Bardsley@arm.com 'IsThreadSync', # Thread synchronization operation. 8410201SAndrew.Bardsley@arm.com 8510201SAndrew.Bardsley@arm.com 'IsSerializing', # Serializes pipeline: won't execute until all 8610201SAndrew.Bardsley@arm.com # older instructions have committed. 8710201SAndrew.Bardsley@arm.com 'IsSerializeBefore', 8810201SAndrew.Bardsley@arm.com 'IsSerializeAfter', 8910201SAndrew.Bardsley@arm.com 'IsMemBarrier', # Is a memory barrier 9010201SAndrew.Bardsley@arm.com 'IsWriteBarrier', # Is a write barrier 9110201SAndrew.Bardsley@arm.com 'IsReadBarrier', # Is a read barrier 9210201SAndrew.Bardsley@arm.com 'IsERET', # <- Causes the IFU to stall (MIPS ISA) 9310201SAndrew.Bardsley@arm.com 9410201SAndrew.Bardsley@arm.com 'IsNonSpeculative', # Should not be executed speculatively 9510201SAndrew.Bardsley@arm.com 'IsQuiesce', # Is a quiesce instruction 9610201SAndrew.Bardsley@arm.com 9710201SAndrew.Bardsley@arm.com 'IsIprAccess', # Accesses IPRs 9810201SAndrew.Bardsley@arm.com 'IsUnverifiable', # Can't be verified by a checker 9910201SAndrew.Bardsley@arm.com 10010201SAndrew.Bardsley@arm.com 'IsSyscall', # Causes a system call to be emulated in syscall 10110201SAndrew.Bardsley@arm.com # emulation mode. 10210201SAndrew.Bardsley@arm.com 10310201SAndrew.Bardsley@arm.com # Flags for microcode 10410201SAndrew.Bardsley@arm.com 'IsMacroop', # Is a macroop containing microops 10510201SAndrew.Bardsley@arm.com 'IsMicroop', # Is a microop 10610201SAndrew.Bardsley@arm.com 'IsDelayedCommit', # This microop doesn't commit right away 10710201SAndrew.Bardsley@arm.com 'IsLastMicroop', # This microop ends a microop sequence 10810201SAndrew.Bardsley@arm.com 'IsFirstMicroop', # This microop begins a microop sequence 10910201SAndrew.Bardsley@arm.com # This flag doesn't do anything yet 11010201SAndrew.Bardsley@arm.com 'IsMicroBranch', # This microop branches within the microcode for 11110201SAndrew.Bardsley@arm.com # a macroop 11210201SAndrew.Bardsley@arm.com 'IsDspOp', 11310935Snilay@cs.wisc.edu 'IsSquashAfter' # Squash all uncommitted state after executed 11410201SAndrew.Bardsley@arm.com ] 115