StaticInstFlags.py revision 10201
19447SAndreas.Sandberg@ARM.com# Copyright (c) 2003-2005 The Regents of The University of Michigan 29447SAndreas.Sandberg@ARM.com# Copyright (c) 2013 Advanced Micro Devices, Inc. 39447SAndreas.Sandberg@ARM.com# All rights reserved. 49447SAndreas.Sandberg@ARM.com# 59447SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 69447SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 79447SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 89447SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 99447SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 109447SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 119447SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 129447SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 139447SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 149447SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 159447SAndreas.Sandberg@ARM.com# 169447SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179447SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189447SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199447SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209447SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219447SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229447SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239447SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249447SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259447SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269447SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279447SAndreas.Sandberg@ARM.com# 289447SAndreas.Sandberg@ARM.com# Authors: Steve Reinhardt 299447SAndreas.Sandberg@ARM.com 309447SAndreas.Sandberg@ARM.comfrom m5.params import * 319447SAndreas.Sandberg@ARM.com 329447SAndreas.Sandberg@ARM.com# Set of boolean static instruction properties. 339447SAndreas.Sandberg@ARM.com# 349447SAndreas.Sandberg@ARM.com# Notes: 359447SAndreas.Sandberg@ARM.com# - The IsInteger and IsFloating flags are based on the class of registers 369447SAndreas.Sandberg@ARM.com# accessed by the instruction. Although most instructions will have exactly 379447SAndreas.Sandberg@ARM.com# one of these two flags set, it is possible for an instruction to have 3812575Sgiacomo.travaglini@arm.com# neither (e.g., direct unconditional branches, memory barriers) or both 3912575Sgiacomo.travaglini@arm.com# (e.g., an FP/int conversion). 409447SAndreas.Sandberg@ARM.com# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set. 4111802Sandreas.sandberg@arm.com# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect 429447SAndreas.Sandberg@ARM.com# Control will be set, and exactly one of IsCondControl or IsUncondControl 4311682Sandreas.hansson@arm.com# will be set. 4411682Sandreas.hansson@arm.com# - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags 459447SAndreas.Sandberg@ARM.com# since in the current model there's no other way for instructions to inject 469447SAndreas.Sandberg@ARM.com# behavior into the pipeline outside of fetch. Once we go to an exec-in-exec 479447SAndreas.Sandberg@ARM.com# CPU model we should be able to get rid of these flags and implement this 489447SAndreas.Sandberg@ARM.com# behavior via the execute() methods. 499447SAndreas.Sandberg@ARM.com 509447SAndreas.Sandberg@ARM.comclass StaticInstFlags(Enum): 519447SAndreas.Sandberg@ARM.com wrapper_name = 'StaticInstFlags' 529447SAndreas.Sandberg@ARM.com wrapper_is_struct = True 539447SAndreas.Sandberg@ARM.com enum_name = 'Flags' 549447SAndreas.Sandberg@ARM.com 559447SAndreas.Sandberg@ARM.com vals = [ 569447SAndreas.Sandberg@ARM.com 'IsNop', # Is a no-op (no effect at all). 579447SAndreas.Sandberg@ARM.com 589447SAndreas.Sandberg@ARM.com 'IsInteger', # References integer regs. 599447SAndreas.Sandberg@ARM.com 'IsFloating', # References FP regs. 609447SAndreas.Sandberg@ARM.com 'IsCC', # References CC regs. 619447SAndreas.Sandberg@ARM.com 629447SAndreas.Sandberg@ARM.com 'IsMemRef', # References memory (load, store, or prefetch) 639447SAndreas.Sandberg@ARM.com 'IsLoad', # Reads from memory (load or prefetch). 649447SAndreas.Sandberg@ARM.com 'IsStore', # Writes to memory. 659447SAndreas.Sandberg@ARM.com 'IsStoreConditional', # Store conditional instruction. 669447SAndreas.Sandberg@ARM.com 'IsIndexed', # Accesses memory with an indexed address 679447SAndreas.Sandberg@ARM.com # computation 689447SAndreas.Sandberg@ARM.com 'IsInstPrefetch', # Instruction-cache prefetch. 699447SAndreas.Sandberg@ARM.com 'IsDataPrefetch', # Data-cache prefetch. 709447SAndreas.Sandberg@ARM.com 719447SAndreas.Sandberg@ARM.com 'IsControl', # Control transfer instruction. 729447SAndreas.Sandberg@ARM.com 'IsDirectControl', # PC relative control transfer. 739447SAndreas.Sandberg@ARM.com 'IsIndirectControl',# Register indirect control transfer. 749447SAndreas.Sandberg@ARM.com 'IsCondControl', # Conditional control transfer. 759447SAndreas.Sandberg@ARM.com 'IsUncondControl', # Unconditional control transfer. 769980Ssteve.reinhardt@amd.com 'IsCall', # Subroutine call. 779447SAndreas.Sandberg@ARM.com 'IsReturn', # Subroutine return. 789447SAndreas.Sandberg@ARM.com 799447SAndreas.Sandberg@ARM.com 'IsCondDelaySlot', # Conditional Delay-Slot Instruction 809447SAndreas.Sandberg@ARM.com 819447SAndreas.Sandberg@ARM.com 'IsThreadSync', # Thread synchronization operation. 829447SAndreas.Sandberg@ARM.com 839447SAndreas.Sandberg@ARM.com 'IsSerializing', # Serializes pipeline: won't execute until all 849447SAndreas.Sandberg@ARM.com # older instructions have committed. 859447SAndreas.Sandberg@ARM.com 'IsSerializeBefore', 869447SAndreas.Sandberg@ARM.com 'IsSerializeAfter', 879447SAndreas.Sandberg@ARM.com 'IsMemBarrier', # Is a memory barrier 889447SAndreas.Sandberg@ARM.com 'IsWriteBarrier', # Is a write barrier 899447SAndreas.Sandberg@ARM.com 'IsReadBarrier', # Is a read barrier 909447SAndreas.Sandberg@ARM.com 'IsERET', # <- Causes the IFU to stall (MIPS ISA) 919447SAndreas.Sandberg@ARM.com 929447SAndreas.Sandberg@ARM.com 'IsNonSpeculative', # Should not be executed speculatively 939447SAndreas.Sandberg@ARM.com 'IsQuiesce', # Is a quiesce instruction 949447SAndreas.Sandberg@ARM.com 959447SAndreas.Sandberg@ARM.com 'IsIprAccess', # Accesses IPRs 969447SAndreas.Sandberg@ARM.com 'IsUnverifiable', # Can't be verified by a checker 979980Ssteve.reinhardt@amd.com 989447SAndreas.Sandberg@ARM.com 'IsSyscall', # Causes a system call to be emulated in syscall 999447SAndreas.Sandberg@ARM.com # emulation mode. 1009447SAndreas.Sandberg@ARM.com 1019447SAndreas.Sandberg@ARM.com # Flags for microcode 1029447SAndreas.Sandberg@ARM.com 'IsMacroop', # Is a macroop containing microops 1039447SAndreas.Sandberg@ARM.com 'IsMicroop', # Is a microop 1049447SAndreas.Sandberg@ARM.com 'IsDelayedCommit', # This microop doesn't commit right away 1059521SAndreas.Sandberg@ARM.com 'IsLastMicroop', # This microop ends a microop sequence 1069447SAndreas.Sandberg@ARM.com 'IsFirstMicroop', # This microop begins a microop sequence 1079980Ssteve.reinhardt@amd.com # This flag doesn't do anything yet 1089980Ssteve.reinhardt@amd.com 'IsMicroBranch', # This microop branches within the microcode for 1099980Ssteve.reinhardt@amd.com # a macroop 11011880Sandreas.sandberg@arm.com 'IsDspOp', 11111988Sandreas.sandberg@arm.com 'IsSquashAfter' # Squash all uncommitted state after executed 1129980Ssteve.reinhardt@amd.com ] 1139447SAndreas.Sandberg@ARM.com