SConscript revision 6994:c6951099a1cb 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33#################################################################
34#
35# Generate StaticInst execute() method signatures.
36#
37# There must be one signature for each CPU model compiled in.
38# Since the set of compiled-in models is flexible, we generate a
39# header containing the appropriate set of signatures on the fly.
40#
41#################################################################
42
43# Template for execute() signature.
44exec_sig_template = '''
45virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
46virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
47{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
48virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
49{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
50virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
51                          Trace::InstRecord *traceData) const
52{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
53'''
54
55mem_ini_sig_template = '''
56virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
57{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
58virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
59'''
60
61mem_comp_sig_template = '''
62virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
63'''
64
65# Generate a temporary CPU list, including the CheckerCPU if
66# it's enabled.  This isn't used for anything else other than StaticInst
67# headers.
68temp_cpu_list = env['CPU_MODELS'][:]
69
70if env['USE_CHECKER']:
71    temp_cpu_list.append('CheckerCPU')
72    SimObject('CheckerCPU.py')
73
74# Generate header.
75def gen_cpu_exec_signatures(target, source, env):
76    f = open(str(target[0]), 'w')
77    print >> f, '''
78#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
79#define __CPU_STATIC_INST_EXEC_SIGS_HH__
80'''
81    for cpu in temp_cpu_list:
82        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
83        print >> f, exec_sig_template % { 'type' : xc_type }
84    print >> f, '''
85#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
86'''
87
88# Generate string that gets printed when header is rebuilt
89def gen_sigs_string(target, source, env):
90    return "Generating static_inst_exec_sigs.hh: " \
91           + ', '.join(temp_cpu_list)
92
93# Add command to generate header to environment.
94env.Command('static_inst_exec_sigs.hh', (),
95            Action(gen_cpu_exec_signatures, gen_sigs_string,
96                   varlist = temp_cpu_list))
97
98env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
99env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
100
101# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
102# and one of these are not being used.
103CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
104
105SimObject('BaseCPU.py')
106SimObject('FuncUnit.py')
107SimObject('ExeTracer.py')
108SimObject('IntelTrace.py')
109SimObject('NativeTrace.py')
110
111Source('activity.cc')
112Source('base.cc')
113Source('cpuevent.cc')
114Source('exetrace.cc')
115Source('func_unit.cc')
116Source('inteltrace.cc')
117Source('nativetrace.cc')
118Source('pc_event.cc')
119Source('quiesce_event.cc')
120Source('static_inst.cc')
121Source('simple_thread.cc')
122Source('thread_context.cc')
123Source('thread_state.cc')
124
125if env['FULL_SYSTEM']:
126    SimObject('IntrControl.py')
127
128    Source('intr_control.cc')
129    Source('profile.cc')
130
131    if env['TARGET_ISA'] == 'sparc':
132        SimObject('LegionTrace.py')
133        Source('legiontrace.cc')
134
135if env['USE_CHECKER']:
136    Source('checker/cpu.cc')
137    TraceFlag('Checker')
138    checker_supports = False
139    for i in CheckerSupportedCPUList:
140        if i in env['CPU_MODELS']:
141            checker_supports = True
142    if not checker_supports:
143        print "Checker only supports CPU models",
144        for i in CheckerSupportedCPUList:
145            print i,
146        print ", please set USE_CHECKER=False or use one of those CPU models"
147        Exit(1)
148
149TraceFlag('Activity')
150TraceFlag('Commit')
151TraceFlag('Context')
152TraceFlag('Decode')
153TraceFlag('DynInst')
154TraceFlag('ExecEnable')
155TraceFlag('ExecCPSeq')
156TraceFlag('ExecEffAddr')
157TraceFlag('ExecFaulting', 'Trace faulting instructions')
158TraceFlag('ExecFetchSeq')
159TraceFlag('ExecOpClass')
160TraceFlag('ExecRegDelta')
161TraceFlag('ExecResult')
162TraceFlag('ExecSpeculative')
163TraceFlag('ExecSymbol')
164TraceFlag('ExecThread')
165TraceFlag('ExecTicks')
166TraceFlag('ExecMicro')
167TraceFlag('ExecMacro')
168TraceFlag('Fetch')
169TraceFlag('IntrControl')
170TraceFlag('PCEvent')
171TraceFlag('Quiesce')
172
173CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
174    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
175CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
176    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
177