SConscript revision 5799
112854Sgabeblack@google.com# -*- mode:python -*- 212854Sgabeblack@google.com 312854Sgabeblack@google.com# Copyright (c) 2006 The Regents of The University of Michigan 412854Sgabeblack@google.com# All rights reserved. 512854Sgabeblack@google.com# 612854Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 712854Sgabeblack@google.com# modification, are permitted provided that the following conditions are 812854Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 912854Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 1012854Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 1112854Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 1212854Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 1312854Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 1412854Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 1512854Sgabeblack@google.com# this software without specific prior written permission. 1612854Sgabeblack@google.com# 1712854Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812854Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912854Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012854Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112854Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212854Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312854Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412854Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512854Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612854Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712854Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812854Sgabeblack@google.com# 2912854Sgabeblack@google.com# Authors: Steve Reinhardt 3012854Sgabeblack@google.com 3113325Sgabeblack@google.comImport('*') 3212854Sgabeblack@google.com 3312854Sgabeblack@google.com################################################################# 3412854Sgabeblack@google.com# 3512854Sgabeblack@google.com# Generate StaticInst execute() method signatures. 3612854Sgabeblack@google.com# 3712854Sgabeblack@google.com# There must be one signature for each CPU model compiled in. 3812854Sgabeblack@google.com# Since the set of compiled-in models is flexible, we generate a 3912854Sgabeblack@google.com# header containing the appropriate set of signatures on the fly. 4012854Sgabeblack@google.com# 4112854Sgabeblack@google.com################################################################# 4212854Sgabeblack@google.com 43# CPU model-specific data is contained in cpu_models.py 44# Convert to SCons File node to get path handling 45models_db = File('cpu_models.py') 46# slurp in contents of file 47execfile(models_db.srcnode().abspath) 48 49# Template for execute() signature. 50exec_sig_template = ''' 51virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; 52virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const 53{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 54virtual Fault completeAcc(Packet *pkt, %s *xc, 55 Trace::InstRecord *traceData) const 56{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 57''' 58 59mem_ini_sig_template = ''' 60virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 61''' 62 63mem_comp_sig_template = ''' 64virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 65''' 66 67# Generate a temporary CPU list, including the CheckerCPU if 68# it's enabled. This isn't used for anything else other than StaticInst 69# headers. 70temp_cpu_list = env['CPU_MODELS'][:] 71 72if env['USE_CHECKER']: 73 temp_cpu_list.append('CheckerCPU') 74 SimObject('CheckerCPU.py') 75 76# Generate header. 77def gen_cpu_exec_signatures(target, source, env): 78 f = open(str(target[0]), 'w') 79 print >> f, ''' 80#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 81#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 82''' 83 for cpu in temp_cpu_list: 84 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 85 print >> f, exec_sig_template % (xc_type, xc_type, xc_type) 86 print >> f, ''' 87#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 88''' 89 90# Generate string that gets printed when header is rebuilt 91def gen_sigs_string(target, source, env): 92 return "Generating static_inst_exec_sigs.hh: " \ 93 + ', '.join(temp_cpu_list) 94 95# Add command to generate header to environment. 96env.Command('static_inst_exec_sigs.hh', models_db, 97 Action(gen_cpu_exec_signatures, gen_sigs_string, 98 varlist = temp_cpu_list)) 99 100env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 102 103# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 104# and one of these are not being used. 105CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 106 107SimObject('BaseCPU.py') 108SimObject('FuncUnit.py') 109SimObject('ExeTracer.py') 110SimObject('IntelTrace.py') 111 112Source('activity.cc') 113Source('base.cc') 114Source('cpuevent.cc') 115Source('exetrace.cc') 116Source('func_unit.cc') 117Source('inteltrace.cc') 118Source('pc_event.cc') 119Source('quiesce_event.cc') 120Source('static_inst.cc') 121Source('simple_thread.cc') 122Source('thread_context.cc') 123Source('thread_state.cc') 124 125if env['FULL_SYSTEM']: 126 SimObject('IntrControl.py') 127 128 Source('intr_control.cc') 129 Source('profile.cc') 130 131 if env['TARGET_ISA'] == 'sparc': 132 SimObject('LegionTrace.py') 133 Source('legiontrace.cc') 134 135if env['TARGET_ISA'] == 'x86': 136 SimObject('NativeTrace.py') 137 Source('nativetrace.cc') 138 139if env['USE_CHECKER']: 140 Source('checker/cpu.cc') 141 TraceFlag('Checker') 142 checker_supports = False 143 for i in CheckerSupportedCPUList: 144 if i in env['CPU_MODELS']: 145 checker_supports = True 146 if not checker_supports: 147 print "Checker only supports CPU models", 148 for i in CheckerSupportedCPUList: 149 print i, 150 print ", please set USE_CHECKER=False or use one of those CPU models" 151 Exit(1) 152 153TraceFlag('Activity') 154TraceFlag('Commit') 155TraceFlag('Context') 156TraceFlag('Decode') 157TraceFlag('DynInst') 158TraceFlag('ExecEnable') 159TraceFlag('ExecCPSeq') 160TraceFlag('ExecEffAddr') 161TraceFlag('ExecFetchSeq') 162TraceFlag('ExecOpClass') 163TraceFlag('ExecRegDelta') 164TraceFlag('ExecResult') 165TraceFlag('ExecSpeculative') 166TraceFlag('ExecSymbol') 167TraceFlag('ExecThread') 168TraceFlag('ExecTicks') 169TraceFlag('ExecMicro') 170TraceFlag('ExecMacro') 171TraceFlag('Fetch') 172TraceFlag('IntrControl') 173TraceFlag('PCEvent') 174TraceFlag('Quiesce') 175 176CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 177 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ]) 178