SConscript revision 13325
19363Snilay@cs.wisc.edu# -*- mode:python -*-
29363Snilay@cs.wisc.edu
39363Snilay@cs.wisc.edu# Copyright (c) 2006 The Regents of The University of Michigan
49363Snilay@cs.wisc.edu# All rights reserved.
59363Snilay@cs.wisc.edu#
69363Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without
79363Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are
89363Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright
99363Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer;
109363Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright
119363Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the
129363Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution;
139363Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its
149363Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from
159363Snilay@cs.wisc.edu# this software without specific prior written permission.
169363Snilay@cs.wisc.edu#
179363Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
189363Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
199363Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
209363Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
219363Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
229363Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
239363Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
249363Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
259363Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
269363Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
279363Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
289363Snilay@cs.wisc.edu#
299363Snilay@cs.wisc.edu# Authors: Steve Reinhardt
309363Snilay@cs.wisc.edu
319363Snilay@cs.wisc.eduImport('*')
329363Snilay@cs.wisc.edu
339363Snilay@cs.wisc.eduif env['TARGET_ISA'] == 'null':
349363Snilay@cs.wisc.edu    SimObject('IntrControl.py')
359363Snilay@cs.wisc.edu    Source('intr_control_noisa.cc')
3610301Snilay@cs.wisc.edu    Return()
3710301Snilay@cs.wisc.edu
3810301Snilay@cs.wisc.edu# Only build the protocol buffer instructions tracer if we have protobuf support
3910301Snilay@cs.wisc.eduif env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
409363Snilay@cs.wisc.edu    SimObject('InstPBTrace.py')
4110301Snilay@cs.wisc.edu    Source('inst_pb_trace.cc')
4210301Snilay@cs.wisc.edu
4310301Snilay@cs.wisc.eduSimObject('CheckerCPU.py')
4410301Snilay@cs.wisc.edu
4510301Snilay@cs.wisc.eduSimObject('BaseCPU.py')
4610301Snilay@cs.wisc.eduSimObject('CPUTracers.py')
4710301Snilay@cs.wisc.eduSimObject('FuncUnit.py')
4810301Snilay@cs.wisc.eduSimObject('IntrControl.py')
4910301Snilay@cs.wisc.eduSimObject('TimingExpr.py')
5010301Snilay@cs.wisc.edu
519363Snilay@cs.wisc.eduSource('activity.cc')
5210301Snilay@cs.wisc.eduSource('base.cc')
5310301Snilay@cs.wisc.eduSource('cpuevent.cc')
54Source('exetrace.cc')
55Source('exec_context.cc')
56Source('func_unit.cc')
57Source('inteltrace.cc')
58Source('intr_control.cc')
59Source('nativetrace.cc')
60Source('pc_event.cc')
61Source('profile.cc')
62Source('quiesce_event.cc')
63Source('reg_class.cc')
64Source('static_inst.cc')
65Source('simple_thread.cc')
66Source('thread_context.cc')
67Source('thread_state.cc')
68Source('timing_expr.cc')
69
70SimObject('DummyChecker.py')
71SimObject('StaticInstFlags.py')
72Source('checker/cpu.cc')
73Source('dummy_checker.cc')
74DebugFlag('Checker')
75
76DebugFlag('Activity')
77DebugFlag('Commit')
78DebugFlag('Context')
79DebugFlag('Decode')
80DebugFlag('DynInst')
81DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
82DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
83DebugFlag('ExecEffAddr', 'Format: Include effective address')
84DebugFlag('ExecFaulting', 'Trace faulting instructions')
85DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
86DebugFlag('ExecOpClass', 'Format: Include operand class')
87DebugFlag('ExecRegDelta')
88DebugFlag('ExecResult', 'Format: Include results from execution')
89DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
90DebugFlag('ExecThread', 'Format: Include thread ID in trace')
91DebugFlag('ExecTicks', 'Format: Include tick count')
92DebugFlag('ExecMicro', 'Filter: Include microops')
93DebugFlag('ExecMacro', 'Filter: Include macroops')
94DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
95DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
96DebugFlag('ExecAsid', 'Format: Include ASID in trace')
97DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
98DebugFlag('Fetch')
99DebugFlag('IntrControl')
100DebugFlag('O3PipeView')
101DebugFlag('PCEvent')
102DebugFlag('Quiesce')
103DebugFlag('Mwait')
104
105CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
106    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
107    'ExecResult', 'ExecSymbol', 'ExecThread',
108    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
109    'ExecAsid', 'ExecFlags' ])
110CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
111    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
112    'ExecFaulting', 'ExecUser', 'ExecKernel' ])
113CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
114    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting',
115    'ExecUser', 'ExecKernel' ])
116