SConscript revision 10529:05b5a6cf3521 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'null':
34    SimObject('IntrControl.py')
35    Source('intr_control_noisa.cc')
36    Return()
37
38SimObject('CheckerCPU.py')
39
40SimObject('BaseCPU.py')
41SimObject('FuncUnit.py')
42SimObject('ExeTracer.py')
43SimObject('IntelTrace.py')
44SimObject('IntrControl.py')
45SimObject('NativeTrace.py')
46SimObject('TimingExpr.py')
47
48Source('activity.cc')
49Source('base.cc')
50Source('cpuevent.cc')
51Source('exetrace.cc')
52Source('exec_context.cc')
53Source('func_unit.cc')
54Source('inteltrace.cc')
55Source('intr_control.cc')
56Source('nativetrace.cc')
57Source('pc_event.cc')
58Source('profile.cc')
59Source('quiesce_event.cc')
60Source('reg_class.cc')
61Source('static_inst.cc')
62Source('simple_thread.cc')
63Source('thread_context.cc')
64Source('thread_state.cc')
65Source('timing_expr.cc')
66
67if env['TARGET_ISA'] == 'sparc':
68    SimObject('LegionTrace.py')
69    Source('legiontrace.cc')
70
71SimObject('DummyChecker.py')
72SimObject('StaticInstFlags.py')
73Source('checker/cpu.cc')
74Source('dummy_checker.cc')
75DebugFlag('Checker')
76
77DebugFlag('Activity')
78DebugFlag('Commit')
79DebugFlag('Context')
80DebugFlag('Decode')
81DebugFlag('DynInst')
82DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
83DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
84DebugFlag('ExecEffAddr', 'Format: Include effective address')
85DebugFlag('ExecFaulting', 'Trace faulting instructions')
86DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
87DebugFlag('ExecOpClass', 'Format: Include operand class')
88DebugFlag('ExecRegDelta')
89DebugFlag('ExecResult', 'Format: Include results from execution')
90DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
91DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
92DebugFlag('ExecThread', 'Format: Include thread ID in trace')
93DebugFlag('ExecTicks', 'Format: Include tick count')
94DebugFlag('ExecMicro', 'Filter: Include microops')
95DebugFlag('ExecMacro', 'Filter: Include macroops')
96DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
97DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
98DebugFlag('ExecAsid', 'Format: Include ASID in trace')
99DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
100DebugFlag('Fetch')
101DebugFlag('IntrControl')
102DebugFlag('O3PipeView')
103DebugFlag('PCEvent')
104DebugFlag('Quiesce')
105DebugFlag('Mwait')
106
107CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
108    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
109    'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
110    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
111    'ExecAsid', 'ExecFlags' ])
112CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
113    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
114    'ExecUser', 'ExecKernel' ])
115CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
116    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
117    'ExecUser', 'ExecKernel' ])
118