SConscript revision 5863
12086SN/A# -*- mode:python -*- 22086SN/A 32086SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42086SN/A# All rights reserved. 52086SN/A# 62086SN/A# Redistribution and use in source and binary forms, with or without 72086SN/A# modification, are permitted provided that the following conditions are 82086SN/A# met: redistributions of source code must retain the above copyright 92086SN/A# notice, this list of conditions and the following disclaimer; 102086SN/A# redistributions in binary form must reproduce the above copyright 112086SN/A# notice, this list of conditions and the following disclaimer in the 122086SN/A# documentation and/or other materials provided with the distribution; 132086SN/A# neither the name of the copyright holders nor the names of its 142086SN/A# contributors may be used to endorse or promote products derived from 152086SN/A# this software without specific prior written permission. 162086SN/A# 172086SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182086SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192086SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202086SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212086SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222086SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232086SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242086SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252086SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262086SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272086SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu 312686Sksewell@umich.eduImport('*') 322086SN/A 332086SN/A################################################################# 342086SN/A# 352086SN/A# Generate StaticInst execute() method signatures. 362086SN/A# 372086SN/A# There must be one signature for each CPU model compiled in. 382086SN/A# Since the set of compiled-in models is flexible, we generate a 392086SN/A# header containing the appropriate set of signatures on the fly. 402086SN/A# 412086SN/A################################################################# 422086SN/A 432086SN/A# CPU model-specific data is contained in cpu_models.py 442086SN/A# Convert to SCons File node to get path handling 452086SN/Amodels_db = File('cpu_models.py') 462086SN/A# slurp in contents of file 472152SN/Aexecfile(models_db.srcnode().abspath) 482152SN/A 492152SN/A# Template for execute() signature. 502686Sksewell@umich.eduexec_sig_template = ''' 512086SN/Avirtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; 522086SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const 532086SN/A{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 542152SN/Avirtual Fault completeAcc(Packet *pkt, %s *xc, 552745Sksewell@umich.edu Trace::InstRecord *traceData) const 562086SN/A{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 572086SN/A''' 582086SN/A 592152SN/Amem_ini_sig_template = ''' 602597SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 612597SN/A''' 622447SN/A 632086SN/Amem_comp_sig_template = ''' 642086SN/Avirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 652086SN/A''' 662152SN/A 672086SN/A# Generate a temporary CPU list, including the CheckerCPU if 682086SN/A# it's enabled. This isn't used for anything else other than StaticInst 692152SN/A# headers. 702086SN/Atemp_cpu_list = env['CPU_MODELS'][:] 712152SN/A 722086SN/Aif env['USE_CHECKER']: 732152SN/A temp_cpu_list.append('CheckerCPU') 742152SN/A SimObject('CheckerCPU.py') 752152SN/A 762152SN/A# Generate header. 772152SN/Adef gen_cpu_exec_signatures(target, source, env): 782152SN/A f = open(str(target[0]), 'w') 792152SN/A print >> f, ''' 802152SN/A#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 812152SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 822086SN/A''' 832086SN/A for cpu in temp_cpu_list: 84 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 85 print >> f, exec_sig_template % (xc_type, xc_type, xc_type) 86 print >> f, ''' 87#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 88''' 89 90# Generate string that gets printed when header is rebuilt 91def gen_sigs_string(target, source, env): 92 return "Generating static_inst_exec_sigs.hh: " \ 93 + ', '.join(temp_cpu_list) 94 95# Add command to generate header to environment. 96env.Command('static_inst_exec_sigs.hh', models_db, 97 Action(gen_cpu_exec_signatures, gen_sigs_string, 98 varlist = temp_cpu_list)) 99 100env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 102 103# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 104# and one of these are not being used. 105CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 106 107SimObject('BaseCPU.py') 108SimObject('FuncUnit.py') 109SimObject('ExeTracer.py') 110SimObject('IntelTrace.py') 111 112Source('activity.cc') 113Source('base.cc') 114Source('cpuevent.cc') 115Source('exetrace.cc') 116Source('func_unit.cc') 117Source('inteltrace.cc') 118Source('pc_event.cc') 119Source('quiesce_event.cc') 120Source('static_inst.cc') 121Source('simple_thread.cc') 122Source('thread_context.cc') 123Source('thread_state.cc') 124 125if env['FULL_SYSTEM']: 126 SimObject('IntrControl.py') 127 128 Source('intr_control.cc') 129 Source('profile.cc') 130 131 if env['TARGET_ISA'] == 'sparc': 132 SimObject('LegionTrace.py') 133 Source('legiontrace.cc') 134 135if env['TARGET_ISA'] == 'x86': 136 SimObject('NativeTrace.py') 137 Source('nativetrace.cc') 138 139if env['USE_CHECKER']: 140 Source('checker/cpu.cc') 141 TraceFlag('Checker') 142 checker_supports = False 143 for i in CheckerSupportedCPUList: 144 if i in env['CPU_MODELS']: 145 checker_supports = True 146 if not checker_supports: 147 print "Checker only supports CPU models", 148 for i in CheckerSupportedCPUList: 149 print i, 150 print ", please set USE_CHECKER=False or use one of those CPU models" 151 Exit(1) 152 153TraceFlag('Activity') 154TraceFlag('Commit') 155TraceFlag('Context') 156TraceFlag('Decode') 157TraceFlag('DynInst') 158TraceFlag('ExecEnable') 159TraceFlag('ExecCPSeq') 160TraceFlag('ExecEffAddr') 161TraceFlag('ExecFetchSeq') 162TraceFlag('ExecOpClass') 163TraceFlag('ExecRegDelta') 164TraceFlag('ExecResult') 165TraceFlag('ExecSpeculative') 166TraceFlag('ExecSymbol') 167TraceFlag('ExecThread') 168TraceFlag('ExecTicks') 169TraceFlag('ExecMicro') 170TraceFlag('ExecMacro') 171TraceFlag('Fetch') 172TraceFlag('IntrControl') 173TraceFlag('PCEvent') 174TraceFlag('Quiesce') 175 176CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 177 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ]) 178