SConscript revision 5773
14202Sbinkertn@umich.edu# -*- mode:python -*-
24202Sbinkertn@umich.edu
34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
44202Sbinkertn@umich.edu# All rights reserved.
54202Sbinkertn@umich.edu#
64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without
74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are
84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright
94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer;
104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright
114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the
124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution;
134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its
144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from
154202Sbinkertn@umich.edu# this software without specific prior written permission.
164202Sbinkertn@umich.edu#
174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
284202Sbinkertn@umich.edu#
294202Sbinkertn@umich.edu# Authors: Steve Reinhardt
304202Sbinkertn@umich.edu
314202Sbinkertn@umich.eduImport('*')
324202Sbinkertn@umich.edu
335952Ssaidi@eecs.umich.edu#################################################################
345952Ssaidi@eecs.umich.edu#
355952Ssaidi@eecs.umich.edu# Generate StaticInst execute() method signatures.
365548Snate@binkert.org#
374202Sbinkertn@umich.edu# There must be one signature for each CPU model compiled in.
387949SAli.Saidi@ARM.com# Since the set of compiled-in models is flexible, we generate a
397067Snate@binkert.org# header containing the appropriate set of signatures on the fly.
404202Sbinkertn@umich.edu#
414202Sbinkertn@umich.edu#################################################################
425882Snate@binkert.org
434202Sbinkertn@umich.edu# CPU model-specific data is contained in cpu_models.py
444550Sbinkertn@umich.edu# Convert to SCons File node to get path handling
454550Sbinkertn@umich.edumodels_db = File('cpu_models.py')
464202Sbinkertn@umich.edu# slurp in contents of file
474202Sbinkertn@umich.eduexecfile(models_db.srcnode().abspath)
484202Sbinkertn@umich.edu
494202Sbinkertn@umich.edu# Template for execute() signature.
504202Sbinkertn@umich.eduexec_sig_template = '''
514202Sbinkertn@umich.eduvirtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
524202Sbinkertn@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
534202Sbinkertn@umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
544202Sbinkertn@umich.eduvirtual Fault completeAcc(Packet *pkt, %s *xc,
555190Ssaidi@eecs.umich.edu                          Trace::InstRecord *traceData) const
564202Sbinkertn@umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
577768SAli.Saidi@ARM.com'''
587768SAli.Saidi@ARM.com
594202Sbinkertn@umich.edumem_ini_sig_template = '''
604202Sbinkertn@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
614202Sbinkertn@umich.edu'''
624202Sbinkertn@umich.edu
634202Sbinkertn@umich.edumem_comp_sig_template = '''
644202Sbinkertn@umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
654202Sbinkertn@umich.edu'''
664202Sbinkertn@umich.edu
674202Sbinkertn@umich.edu# Generate a temporary CPU list, including the CheckerCPU if
684202Sbinkertn@umich.edu# it's enabled.  This isn't used for anything else other than StaticInst
695222Sksewell@umich.edu# headers.
704202Sbinkertn@umich.edutemp_cpu_list = env['CPU_MODELS'][:]
714202Sbinkertn@umich.edu
724202Sbinkertn@umich.eduif env['USE_CHECKER']:
734202Sbinkertn@umich.edu    temp_cpu_list.append('CheckerCPU')
744202Sbinkertn@umich.edu    SimObject('CheckerCPU.py')
754202Sbinkertn@umich.edu
768335Snate@binkert.org# Generate header.
778335Snate@binkert.orgdef gen_cpu_exec_signatures(target, source, env):
788335Snate@binkert.org    f = open(str(target[0]), 'w')
798335Snate@binkert.org    print >> f, '''
808335Snate@binkert.org#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
818335Snate@binkert.org#define __CPU_STATIC_INST_EXEC_SIGS_HH__
828335Snate@binkert.org'''
838335Snate@binkert.org    for cpu in temp_cpu_list:
848335Snate@binkert.org        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
858335Snate@binkert.org        print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
868335Snate@binkert.org    print >> f, '''
878335Snate@binkert.org#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
885192Ssaidi@eecs.umich.edu'''
895800Snate@binkert.org
905800Snate@binkert.org# Generate string that gets printed when header is rebuilt
915800Snate@binkert.orgdef gen_sigs_string(target, source, env):
925800Snate@binkert.org    return "Generating static_inst_exec_sigs.hh: " \
935952Ssaidi@eecs.umich.edu           + ', '.join(temp_cpu_list)
945952Ssaidi@eecs.umich.edu
955952Ssaidi@eecs.umich.edu# Add command to generate header to environment.
96env.Command('static_inst_exec_sigs.hh', models_db,
97            Action(gen_cpu_exec_signatures, gen_sigs_string,
98                   varlist = temp_cpu_list))
99
100env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
102
103# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
104# and one of these are not being used.
105CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
106
107SimObject('BaseCPU.py')
108SimObject('FuncUnit.py')
109SimObject('ExeTracer.py')
110SimObject('IntelTrace.py')
111
112Source('activity.cc')
113Source('base.cc')
114Source('cpuevent.cc')
115Source('exetrace.cc')
116Source('func_unit.cc')
117Source('inteltrace.cc')
118Source('pc_event.cc')
119Source('quiesce_event.cc')
120Source('static_inst.cc')
121Source('simple_thread.cc')
122Source('thread_context.cc')
123Source('thread_state.cc')
124
125if env['FULL_SYSTEM']:
126    SimObject('IntrControl.py')
127
128    Source('intr_control.cc')
129    Source('profile.cc')
130
131    if env['TARGET_ISA'] == 'sparc':
132        SimObject('LegionTrace.py')
133        Source('legiontrace.cc')
134
135if env['TARGET_ISA'] == 'x86':
136    SimObject('NativeTrace.py')
137    Source('nativetrace.cc')
138
139if env['USE_CHECKER']:
140    Source('checker/cpu.cc')
141    TraceFlag('Checker')
142    checker_supports = False
143    for i in CheckerSupportedCPUList:
144        if i in env['CPU_MODELS']:
145            checker_supports = True
146    if not checker_supports:
147        print "Checker only supports CPU models",
148        for i in CheckerSupportedCPUList:
149            print i,
150        print ", please set USE_CHECKER=False or use one of those CPU models"
151        Exit(1)
152# Workaround for bug in SCons version > 0.97d20071212
153# Scons bug id: 2006 M5 Bug id: 308
154else:
155    Dir('checker')
156
157TraceFlag('Activity')
158TraceFlag('Commit')
159TraceFlag('Context')
160TraceFlag('Decode')
161TraceFlag('DynInst')
162TraceFlag('ExecEnable')
163TraceFlag('ExecCPSeq')
164TraceFlag('ExecEffAddr')
165TraceFlag('ExecFetchSeq')
166TraceFlag('ExecOpClass')
167TraceFlag('ExecRegDelta')
168TraceFlag('ExecResult')
169TraceFlag('ExecSpeculative')
170TraceFlag('ExecSymbol')
171TraceFlag('ExecThread')
172TraceFlag('ExecTicks')
173TraceFlag('Fetch')
174TraceFlag('IntrControl')
175TraceFlag('PCEvent')
176TraceFlag('Quiesce')
177
178CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
179    'ExecEffAddr', 'ExecResult', 'ExecSymbol' ])
180