SConscript revision 5522
12086SN/A# -*- mode:python -*- 22086SN/A 32086SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42086SN/A# All rights reserved. 52086SN/A# 62086SN/A# Redistribution and use in source and binary forms, with or without 72086SN/A# modification, are permitted provided that the following conditions are 82086SN/A# met: redistributions of source code must retain the above copyright 92086SN/A# notice, this list of conditions and the following disclaimer; 102086SN/A# redistributions in binary form must reproduce the above copyright 112086SN/A# notice, this list of conditions and the following disclaimer in the 122086SN/A# documentation and/or other materials provided with the distribution; 132086SN/A# neither the name of the copyright holders nor the names of its 142086SN/A# contributors may be used to endorse or promote products derived from 152086SN/A# this software without specific prior written permission. 162086SN/A# 172086SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182086SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192086SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202086SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212086SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222086SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232086SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242086SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252086SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262086SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272086SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu 312086SN/AImport('*') 324202Sbinkertn@umich.edu 332086SN/A################################################################# 344202Sbinkertn@umich.edu# 355403Shines@cs.fsu.edu# Generate StaticInst execute() method signatures. 365403Shines@cs.fsu.edu# 375403Shines@cs.fsu.edu# There must be one signature for each CPU model compiled in. 385403Shines@cs.fsu.edu# Since the set of compiled-in models is flexible, we generate a 394202Sbinkertn@umich.edu# header containing the appropriate set of signatures on the fly. 404202Sbinkertn@umich.edu# 414202Sbinkertn@umich.edu################################################################# 424202Sbinkertn@umich.edu 434202Sbinkertn@umich.edu# CPU model-specific data is contained in cpu_models.py 444997Sgblack@eecs.umich.edu# Convert to SCons File node to get path handling 454202Sbinkertn@umich.edumodels_db = File('cpu_models.py') 464202Sbinkertn@umich.edu# slurp in contents of file 474997Sgblack@eecs.umich.eduexecfile(models_db.srcnode().abspath) 484826Ssaidi@eecs.umich.edu 492086SN/A# Template for execute() signature. 504997Sgblack@eecs.umich.eduexec_sig_template = ''' 515192Ssaidi@eecs.umich.eduvirtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; 524997Sgblack@eecs.umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const 534202Sbinkertn@umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 544486Sbinkertn@umich.eduvirtual Fault completeAcc(Packet *pkt, %s *xc, 555647Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 564486Sbinkertn@umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 575647Sgblack@eecs.umich.edu''' 584202Sbinkertn@umich.edu 594202Sbinkertn@umich.edumem_ini_sig_template = ''' 604202Sbinkertn@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 614202Sbinkertn@umich.edu''' 624202Sbinkertn@umich.edu 634202Sbinkertn@umich.edumem_comp_sig_template = ''' 642086SN/Avirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 654202Sbinkertn@umich.edu''' 664202Sbinkertn@umich.edu 674202Sbinkertn@umich.edu# Generate a temporary CPU list, including the CheckerCPU if 682086SN/A# it's enabled. This isn't used for anything else other than StaticInst 694202Sbinkertn@umich.edu# headers. 704202Sbinkertn@umich.edutemp_cpu_list = env['CPU_MODELS'][:] 712086SN/A 724202Sbinkertn@umich.eduif env['USE_CHECKER']: 734202Sbinkertn@umich.edu temp_cpu_list.append('CheckerCPU') 744202Sbinkertn@umich.edu 754202Sbinkertn@umich.edu# Generate header. 764202Sbinkertn@umich.edudef gen_cpu_exec_signatures(target, source, env): 774202Sbinkertn@umich.edu f = open(str(target[0]), 'w') 78 print >> f, ''' 79#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 80#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 81''' 82 for cpu in temp_cpu_list: 83 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 84 print >> f, exec_sig_template % (xc_type, xc_type, xc_type) 85 print >> f, ''' 86#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 87''' 88 89# Generate string that gets printed when header is rebuilt 90def gen_sigs_string(target, source, env): 91 return "Generating static_inst_exec_sigs.hh: " \ 92 + ', '.join(temp_cpu_list) 93 94# Add command to generate header to environment. 95env.Command('static_inst_exec_sigs.hh', models_db, 96 Action(gen_cpu_exec_signatures, gen_sigs_string, 97 varlist = temp_cpu_list)) 98 99env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 100env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 101 102# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 103# and one of these are not being used. 104CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 105 106SimObject('BaseCPU.py') 107SimObject('FuncUnit.py') 108SimObject('ExeTracer.py') 109SimObject('IntelTrace.py') 110 111Source('activity.cc') 112Source('base.cc') 113Source('cpuevent.cc') 114Source('exetrace.cc') 115Source('func_unit.cc') 116Source('inteltrace.cc') 117Source('pc_event.cc') 118Source('quiesce_event.cc') 119Source('static_inst.cc') 120Source('simple_thread.cc') 121Source('thread_context.cc') 122Source('thread_state.cc') 123 124if env['FULL_SYSTEM']: 125 SimObject('IntrControl.py') 126 127 Source('intr_control.cc') 128 Source('profile.cc') 129 130 if env['TARGET_ISA'] == 'sparc': 131 SimObject('LegionTrace.py') 132 Source('legiontrace.cc') 133 134if env['TARGET_ISA'] == 'x86': 135 SimObject('NativeTrace.py') 136 Source('nativetrace.cc') 137 138if env['USE_CHECKER']: 139 Source('checker/cpu.cc') 140 TraceFlag('Checker') 141 checker_supports = False 142 for i in CheckerSupportedCPUList: 143 if i in env['CPU_MODELS']: 144 checker_supports = True 145 if not checker_supports: 146 print "Checker only supports CPU models", 147 for i in CheckerSupportedCPUList: 148 print i, 149 print ", please set USE_CHECKER=False or use one of those CPU models" 150 Exit(1) 151# Workaround for bug in SCons version > 0.97d20071212 152# Scons bug id: 2006 M5 Bug id: 308 153else: 154 Dir('checker') 155 156TraceFlag('Activity') 157TraceFlag('Commit') 158TraceFlag('Context') 159TraceFlag('Decode') 160TraceFlag('DynInst') 161TraceFlag('ExecEnable') 162TraceFlag('ExecCPSeq') 163TraceFlag('ExecEffAddr') 164TraceFlag('ExecFetchSeq') 165TraceFlag('ExecOpClass') 166TraceFlag('ExecRegDelta') 167TraceFlag('ExecResult') 168TraceFlag('ExecSpeculative') 169TraceFlag('ExecSymbol') 170TraceFlag('ExecThread') 171TraceFlag('ExecTicks') 172TraceFlag('Fetch') 173TraceFlag('IntrControl') 174TraceFlag('PCEvent') 175TraceFlag('Quiesce') 176 177CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 178 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ]) 179