SConscript revision 5217
19852Sandreas.hansson@arm.com# -*- mode:python -*- 28999Suri.wiener@arm.com 38999Suri.wiener@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 48999Suri.wiener@arm.com# All rights reserved. 58999Suri.wiener@arm.com# 68999Suri.wiener@arm.com# Redistribution and use in source and binary forms, with or without 78999Suri.wiener@arm.com# modification, are permitted provided that the following conditions are 88999Suri.wiener@arm.com# met: redistributions of source code must retain the above copyright 98999Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer; 108999Suri.wiener@arm.com# redistributions in binary form must reproduce the above copyright 118999Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer in the 128999Suri.wiener@arm.com# documentation and/or other materials provided with the distribution; 138999Suri.wiener@arm.com# neither the name of the copyright holders nor the names of its 148999Suri.wiener@arm.com# contributors may be used to endorse or promote products derived from 158999Suri.wiener@arm.com# this software without specific prior written permission. 168999Suri.wiener@arm.com# 178999Suri.wiener@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 188999Suri.wiener@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 198999Suri.wiener@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 208999Suri.wiener@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 218999Suri.wiener@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 228999Suri.wiener@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 238999Suri.wiener@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 248999Suri.wiener@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 258999Suri.wiener@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 268999Suri.wiener@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 278999Suri.wiener@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 288999Suri.wiener@arm.com# 298999Suri.wiener@arm.com# Authors: Steve Reinhardt 308999Suri.wiener@arm.com 318999Suri.wiener@arm.comImport('*') 328999Suri.wiener@arm.com 338999Suri.wiener@arm.com################################################################# 348999Suri.wiener@arm.com# 358999Suri.wiener@arm.com# Generate StaticInst execute() method signatures. 368999Suri.wiener@arm.com# 378999Suri.wiener@arm.com# There must be one signature for each CPU model compiled in. 3811418Ssascha.bischoff@arm.com# Since the set of compiled-in models is flexible, we generate a 398999Suri.wiener@arm.com# header containing the appropriate set of signatures on the fly. 408999Suri.wiener@arm.com# 418999Suri.wiener@arm.com################################################################# 428999Suri.wiener@arm.com 438999Suri.wiener@arm.com# CPU model-specific data is contained in cpu_models.py 448999Suri.wiener@arm.com# Convert to SCons File node to get path handling 459852Sandreas.hansson@arm.commodels_db = File('cpu_models.py') 469852Sandreas.hansson@arm.com# slurp in contents of file 479852Sandreas.hansson@arm.comexecfile(models_db.srcnode().abspath) 489852Sandreas.hansson@arm.com 499852Sandreas.hansson@arm.com# Template for execute() signature. 509852Sandreas.hansson@arm.comexec_sig_template = ''' 519852Sandreas.hansson@arm.comvirtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; 529852Sandreas.hansson@arm.comvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const 539852Sandreas.hansson@arm.com{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 549852Sandreas.hansson@arm.comvirtual Fault completeAcc(Packet *pkt, %s *xc, 558999Suri.wiener@arm.com Trace::InstRecord *traceData) const 568999Suri.wiener@arm.com{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 578999Suri.wiener@arm.com''' 588999Suri.wiener@arm.com 598999Suri.wiener@arm.commem_ini_sig_template = ''' 608999Suri.wiener@arm.comvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 618999Suri.wiener@arm.com''' 6210176Ssascha.bischoff@arm.com 639528Ssascha.bischoff@arm.commem_comp_sig_template = ''' 648999Suri.wiener@arm.comvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 658999Suri.wiener@arm.com''' 668999Suri.wiener@arm.com 678999Suri.wiener@arm.com# Generate a temporary CPU list, including the CheckerCPU if 688999Suri.wiener@arm.com# it's enabled. This isn't used for anything else other than StaticInst 698999Suri.wiener@arm.com# headers. 708999Suri.wiener@arm.comtemp_cpu_list = env['CPU_MODELS'][:] 718999Suri.wiener@arm.com 728999Suri.wiener@arm.comif env['USE_CHECKER']: 738999Suri.wiener@arm.com temp_cpu_list.append('CheckerCPU') 748999Suri.wiener@arm.com 758999Suri.wiener@arm.com# Generate header. 769852Sandreas.hansson@arm.comdef gen_cpu_exec_signatures(target, source, env): 779852Sandreas.hansson@arm.com f = open(str(target[0]), 'w') 788999Suri.wiener@arm.com print >> f, ''' 798999Suri.wiener@arm.com#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 808999Suri.wiener@arm.com#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 818999Suri.wiener@arm.com''' 828999Suri.wiener@arm.com for cpu in temp_cpu_list: 838999Suri.wiener@arm.com xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 848999Suri.wiener@arm.com print >> f, exec_sig_template % (xc_type, xc_type, xc_type) 858999Suri.wiener@arm.com print >> f, ''' 868999Suri.wiener@arm.com#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 878999Suri.wiener@arm.com''' 888999Suri.wiener@arm.com 898999Suri.wiener@arm.com# Generate string that gets printed when header is rebuilt 908999Suri.wiener@arm.comdef gen_sigs_string(target, source, env): 918999Suri.wiener@arm.com return "Generating static_inst_exec_sigs.hh: " \ 928999Suri.wiener@arm.com + ', '.join(temp_cpu_list) 938999Suri.wiener@arm.com 948999Suri.wiener@arm.com# Add command to generate header to environment. 958999Suri.wiener@arm.comenv.Command('static_inst_exec_sigs.hh', models_db, 968999Suri.wiener@arm.com Action(gen_cpu_exec_signatures, gen_sigs_string, 978999Suri.wiener@arm.com varlist = temp_cpu_list)) 988999Suri.wiener@arm.com 998999Suri.wiener@arm.comenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 1008999Suri.wiener@arm.comenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1018999Suri.wiener@arm.com 1028999Suri.wiener@arm.com# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1038999Suri.wiener@arm.com# and one of these are not being used. 1048999Suri.wiener@arm.comCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1058999Suri.wiener@arm.com 1068999Suri.wiener@arm.comSimObject('BaseCPU.py') 1078999Suri.wiener@arm.comSimObject('FuncUnit.py') 1088999Suri.wiener@arm.comSimObject('ExeTracer.py') 1098999Suri.wiener@arm.comSimObject('IntelTrace.py') 1108999Suri.wiener@arm.com 11110176Ssascha.bischoff@arm.comSource('activity.cc') 1128999Suri.wiener@arm.comSource('base.cc') 1138999Suri.wiener@arm.comSource('cpuevent.cc') 1148999Suri.wiener@arm.comSource('exetrace.cc') 1158999Suri.wiener@arm.comSource('func_unit.cc') 1168999Suri.wiener@arm.comSource('inteltrace.cc') 1178999Suri.wiener@arm.comSource('pc_event.cc') 1188999Suri.wiener@arm.comSource('quiesce_event.cc') 1198999Suri.wiener@arm.comSource('static_inst.cc') 1208999Suri.wiener@arm.comSource('simple_thread.cc') 1218999Suri.wiener@arm.comSource('thread_context.cc') 1228999Suri.wiener@arm.comSource('thread_state.cc') 1238999Suri.wiener@arm.com 1248999Suri.wiener@arm.comif env['FULL_SYSTEM']: 1258999Suri.wiener@arm.com SimObject('IntrControl.py') 1268999Suri.wiener@arm.com 1278999Suri.wiener@arm.com Source('intr_control.cc') 1288999Suri.wiener@arm.com Source('profile.cc') 1298999Suri.wiener@arm.com 1308999Suri.wiener@arm.com if env['TARGET_ISA'] == 'sparc': 1318999Suri.wiener@arm.com SimObject('LegionTrace.py') 1328999Suri.wiener@arm.com Source('legiontrace.cc') 1338999Suri.wiener@arm.com 1349854Sandreas.hansson@arm.comif env['TARGET_ISA'] == 'x86': 1359854Sandreas.hansson@arm.com SimObject('NativeTrace.py') 1369854Sandreas.hansson@arm.com Source('nativetrace.cc') 1379854Sandreas.hansson@arm.com 1389854Sandreas.hansson@arm.comif env['USE_CHECKER']: 1399854Sandreas.hansson@arm.com Source('checker/cpu.cc') 1409854Sandreas.hansson@arm.com TraceFlag('Checker') 1419854Sandreas.hansson@arm.com checker_supports = False 1429854Sandreas.hansson@arm.com for i in CheckerSupportedCPUList: 1439854Sandreas.hansson@arm.com if i in env['CPU_MODELS']: 1449854Sandreas.hansson@arm.com checker_supports = True 1458999Suri.wiener@arm.com if not checker_supports: 1468999Suri.wiener@arm.com print "Checker only supports CPU models", 1478999Suri.wiener@arm.com for i in CheckerSupportedCPUList: 1488999Suri.wiener@arm.com print i, 1499854Sandreas.hansson@arm.com print ", please set USE_CHECKER=False or use one of those CPU models" 1508999Suri.wiener@arm.com Exit(1) 1518999Suri.wiener@arm.com 1529853Sandreas.hansson@arm.comTraceFlag('Activity') 1538999Suri.wiener@arm.comTraceFlag('Commit') 1548999Suri.wiener@arm.comTraceFlag('Context') 1558999Suri.wiener@arm.comTraceFlag('Decode') 1568999Suri.wiener@arm.comTraceFlag('DynInst') 1578999Suri.wiener@arm.comTraceFlag('ExecEnable') 1588999Suri.wiener@arm.comTraceFlag('ExecCPSeq') 1598999Suri.wiener@arm.comTraceFlag('ExecEffAddr') 1608999Suri.wiener@arm.comTraceFlag('ExecFetchSeq') 1618999Suri.wiener@arm.comTraceFlag('ExecOpClass') 1628999Suri.wiener@arm.comTraceFlag('ExecRegDelta') 1638999Suri.wiener@arm.comTraceFlag('ExecResult') 1648999Suri.wiener@arm.comTraceFlag('ExecSpeculative') 1659853Sandreas.hansson@arm.comTraceFlag('ExecSymbol') 1668999Suri.wiener@arm.comTraceFlag('ExecThread') 1678999Suri.wiener@arm.comTraceFlag('ExecTicks') 1688999Suri.wiener@arm.comTraceFlag('Fetch') 1698999Suri.wiener@arm.comTraceFlag('IntrControl') 1708999Suri.wiener@arm.comTraceFlag('PCEvent') 1719853Sandreas.hansson@arm.comTraceFlag('Quiesce') 1729853Sandreas.hansson@arm.com 1739853Sandreas.hansson@arm.comCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1749853Sandreas.hansson@arm.com 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ]) 1759853Sandreas.hansson@arm.com