SConscript revision 10664 
110994Sandreas.sandberg@arm.com# -*- mode:python -*-
210994Sandreas.sandberg@arm.com
310994Sandreas.sandberg@arm.com# Copyright (c) 2006 The Regents of The University of Michigan
410994Sandreas.sandberg@arm.com# All rights reserved.
510994Sandreas.sandberg@arm.com#
610994Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without
710994Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are
810994Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright
910994Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer;
1010994Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright
1110994Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the
1210994Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution;
1310994Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its
1410994Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from
1510994Sandreas.sandberg@arm.com# this software without specific prior written permission.
1610994Sandreas.sandberg@arm.com#
1710994Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1810994Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1910994Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2010994Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2110994Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2210994Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2310994Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2410994Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2510994Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2610994Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2710994Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2810994Sandreas.sandberg@arm.com#
2910994Sandreas.sandberg@arm.com# Authors: Steve Reinhardt
3010994Sandreas.sandberg@arm.com
3110994Sandreas.sandberg@arm.comImport('*')
3210994Sandreas.sandberg@arm.com
3310994Sandreas.sandberg@arm.comif env['TARGET_ISA'] == 'null':
3410994Sandreas.sandberg@arm.com    SimObject('IntrControl.py')
3510994Sandreas.sandberg@arm.com    Source('intr_control_noisa.cc')
3610994Sandreas.sandberg@arm.com    Return()
3710994Sandreas.sandberg@arm.com
3810994Sandreas.sandberg@arm.comSimObject('CheckerCPU.py')
3910994Sandreas.sandberg@arm.com
4010994Sandreas.sandberg@arm.comSimObject('BaseCPU.py')
4110994Sandreas.sandberg@arm.comSimObject('CPUTracers.py')
4210994Sandreas.sandberg@arm.comSimObject('FuncUnit.py')
4310994Sandreas.sandberg@arm.comSimObject('IntrControl.py')
4410995Sandreas.sandberg@arm.comSimObject('TimingExpr.py')
4510995Sandreas.sandberg@arm.com
4610995Sandreas.sandberg@arm.comSource('activity.cc')
47Source('base.cc')
48Source('cpuevent.cc')
49Source('exetrace.cc')
50Source('exec_context.cc')
51Source('func_unit.cc')
52Source('inteltrace.cc')
53Source('intr_control.cc')
54Source('nativetrace.cc')
55Source('pc_event.cc')
56Source('profile.cc')
57Source('quiesce_event.cc')
58Source('reg_class.cc')
59Source('static_inst.cc')
60Source('simple_thread.cc')
61Source('thread_context.cc')
62Source('thread_state.cc')
63Source('timing_expr.cc')
64
65SimObject('DummyChecker.py')
66SimObject('StaticInstFlags.py')
67Source('checker/cpu.cc')
68Source('dummy_checker.cc')
69DebugFlag('Checker')
70
71DebugFlag('Activity')
72DebugFlag('Commit')
73DebugFlag('Context')
74DebugFlag('Decode')
75DebugFlag('DynInst')
76DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
77DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
78DebugFlag('ExecEffAddr', 'Format: Include effective address')
79DebugFlag('ExecFaulting', 'Trace faulting instructions')
80DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
81DebugFlag('ExecOpClass', 'Format: Include operand class')
82DebugFlag('ExecRegDelta')
83DebugFlag('ExecResult', 'Format: Include results from execution')
84DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
85DebugFlag('ExecThread', 'Format: Include thread ID in trace')
86DebugFlag('ExecTicks', 'Format: Include tick count')
87DebugFlag('ExecMicro', 'Filter: Include microops')
88DebugFlag('ExecMacro', 'Filter: Include macroops')
89DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
90DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
91DebugFlag('ExecAsid', 'Format: Include ASID in trace')
92DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
93DebugFlag('Fetch')
94DebugFlag('IntrControl')
95DebugFlag('O3PipeView')
96DebugFlag('PCEvent')
97DebugFlag('Quiesce')
98DebugFlag('Mwait')
99
100CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
101    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
102    'ExecResult', 'ExecSymbol', 'ExecThread',
103    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
104    'ExecAsid', 'ExecFlags' ])
105CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
106    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
107    'ExecUser', 'ExecKernel' ])
108CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
109    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
110    'ExecUser', 'ExecKernel' ])
111