SConscript revision 10529 
19363Snilay@cs.wisc.edu# -*- mode:python -*-
29363Snilay@cs.wisc.edu
39363Snilay@cs.wisc.edu# Copyright (c) 2006 The Regents of The University of Michigan
49363Snilay@cs.wisc.edu# All rights reserved.
59363Snilay@cs.wisc.edu#
69363Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without
79363Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are
89363Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright
99363Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer;
109363Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright
119363Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the
129363Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution;
139363Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its
149363Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from
159363Snilay@cs.wisc.edu# this software without specific prior written permission.
169363Snilay@cs.wisc.edu#
179363Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
189363Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
199363Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
209363Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
219363Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
229363Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
239363Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
249363Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
259363Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
269363Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
279363Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
289363Snilay@cs.wisc.edu#
299363Snilay@cs.wisc.edu# Authors: Steve Reinhardt
309363Snilay@cs.wisc.edu
319363Snilay@cs.wisc.eduImport('*')
329363Snilay@cs.wisc.edu
339363Snilay@cs.wisc.eduif env['TARGET_ISA'] == 'null':
349363Snilay@cs.wisc.edu    SimObject('IntrControl.py')
359363Snilay@cs.wisc.edu    Source('intr_control_noisa.cc')
3611052Sandreas.hansson@arm.com    Return()
3710301Snilay@cs.wisc.edu
3810970Sdavid.hashe@amd.comSimObject('CheckerCPU.py')
3910970Sdavid.hashe@amd.com
4010970Sdavid.hashe@amd.comSimObject('BaseCPU.py')
4110301Snilay@cs.wisc.eduSimObject('FuncUnit.py')
429363Snilay@cs.wisc.eduSimObject('ExeTracer.py')
4310301Snilay@cs.wisc.eduSimObject('IntelTrace.py')
4410301Snilay@cs.wisc.eduSimObject('IntrControl.py')
4510970Sdavid.hashe@amd.comSimObject('NativeTrace.py')
4610301Snilay@cs.wisc.eduSimObject('TimingExpr.py')
4710301Snilay@cs.wisc.edu
4810970Sdavid.hashe@amd.comSource('activity.cc')
4910970Sdavid.hashe@amd.comSource('base.cc')
5010301Snilay@cs.wisc.eduSource('cpuevent.cc')
5110301Snilay@cs.wisc.eduSource('exetrace.cc')
5210301Snilay@cs.wisc.eduSource('exec_context.cc')
5310301Snilay@cs.wisc.eduSource('func_unit.cc')
549363Snilay@cs.wisc.eduSource('inteltrace.cc')
5510301Snilay@cs.wisc.eduSource('intr_control.cc')
5610301Snilay@cs.wisc.eduSource('nativetrace.cc')
57Source('pc_event.cc')
58Source('profile.cc')
59Source('quiesce_event.cc')
60Source('reg_class.cc')
61Source('static_inst.cc')
62Source('simple_thread.cc')
63Source('thread_context.cc')
64Source('thread_state.cc')
65Source('timing_expr.cc')
66
67if env['TARGET_ISA'] == 'sparc':
68    SimObject('LegionTrace.py')
69    Source('legiontrace.cc')
70
71SimObject('DummyChecker.py')
72SimObject('StaticInstFlags.py')
73Source('checker/cpu.cc')
74Source('dummy_checker.cc')
75DebugFlag('Checker')
76
77DebugFlag('Activity')
78DebugFlag('Commit')
79DebugFlag('Context')
80DebugFlag('Decode')
81DebugFlag('DynInst')
82DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
83DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
84DebugFlag('ExecEffAddr', 'Format: Include effective address')
85DebugFlag('ExecFaulting', 'Trace faulting instructions')
86DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
87DebugFlag('ExecOpClass', 'Format: Include operand class')
88DebugFlag('ExecRegDelta')
89DebugFlag('ExecResult', 'Format: Include results from execution')
90DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
91DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
92DebugFlag('ExecThread', 'Format: Include thread ID in trace')
93DebugFlag('ExecTicks', 'Format: Include tick count')
94DebugFlag('ExecMicro', 'Filter: Include microops')
95DebugFlag('ExecMacro', 'Filter: Include macroops')
96DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
97DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
98DebugFlag('ExecAsid', 'Format: Include ASID in trace')
99DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
100DebugFlag('Fetch')
101DebugFlag('IntrControl')
102DebugFlag('O3PipeView')
103DebugFlag('PCEvent')
104DebugFlag('Quiesce')
105DebugFlag('Mwait')
106
107CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
108    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
109    'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
110    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
111    'ExecAsid', 'ExecFlags' ])
112CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
113    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
114    'ExecUser', 'ExecKernel' ])
115CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
116    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
117    'ExecUser', 'ExecKernel' ])
118