BaseCPU.py revision 9793
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2005-2008 The Regents of The University of Michigan 14# Copyright (c) 2011 Regents of the University of California 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Nathan Binkert 41# Rick Strong 42# Andreas Hansson 43 44import sys 45 46from m5.defines import buildEnv 47from m5.params import * 48from m5.proxy import * 49 50from Bus import CoherentBus 51from InstTracer import InstTracer 52from ExeTracer import ExeTracer 53from MemObject import MemObject 54from BranchPredictor import BranchPredictor 55from ClockDomain import * 56 57default_tracer = ExeTracer() 58 59if buildEnv['TARGET_ISA'] == 'alpha': 60 from AlphaTLB import AlphaDTB, AlphaITB 61 from AlphaInterrupts import AlphaInterrupts 62 from AlphaISA import AlphaISA 63 isa_class = AlphaISA 64elif buildEnv['TARGET_ISA'] == 'sparc': 65 from SparcTLB import SparcTLB 66 from SparcInterrupts import SparcInterrupts 67 from SparcISA import SparcISA 68 isa_class = SparcISA 69elif buildEnv['TARGET_ISA'] == 'x86': 70 from X86TLB import X86TLB 71 from X86LocalApic import X86LocalApic 72 from X86ISA import X86ISA 73 isa_class = X86ISA 74elif buildEnv['TARGET_ISA'] == 'mips': 75 from MipsTLB import MipsTLB 76 from MipsInterrupts import MipsInterrupts 77 from MipsISA import MipsISA 78 isa_class = MipsISA 79elif buildEnv['TARGET_ISA'] == 'arm': 80 from ArmTLB import ArmTLB 81 from ArmInterrupts import ArmInterrupts 82 from ArmISA import ArmISA 83 isa_class = ArmISA 84elif buildEnv['TARGET_ISA'] == 'power': 85 from PowerTLB import PowerTLB 86 from PowerInterrupts import PowerInterrupts 87 from PowerISA import PowerISA 88 isa_class = PowerISA 89 90class BaseCPU(MemObject): 91 type = 'BaseCPU' 92 abstract = True 93 cxx_header = "cpu/base.hh" 94 95 @classmethod 96 def export_methods(cls, code): 97 code(''' 98 void switchOut(); 99 void takeOverFrom(BaseCPU *cpu); 100 bool switchedOut(); 101 void flushTLBs(); 102 Counter totalInsts(); 103 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 104 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 105''') 106 107 @classmethod 108 def memory_mode(cls): 109 """Which memory mode does this CPU require?""" 110 return 'invalid' 111 112 @classmethod 113 def require_caches(cls): 114 """Does the CPU model require caches? 115 116 Some CPU models might make assumptions that require them to 117 have caches. 118 """ 119 return False 120 121 @classmethod 122 def support_take_over(cls): 123 """Does the CPU model support CPU takeOverFrom?""" 124 return False 125 126 def takeOverFrom(self, old_cpu): 127 self._ccObject.takeOverFrom(old_cpu._ccObject) 128 129 130 system = Param.System(Parent.any, "system object") 131 cpu_id = Param.Int(-1, "CPU identifier") 132 numThreads = Param.Unsigned(1, "number of HW thread contexts") 133 134 function_trace = Param.Bool(False, "Enable function trace") 135 function_trace_start = Param.Tick(0, "Tick to start function trace") 136 137 checker = Param.BaseCPU(NULL, "checker CPU") 138 139 do_checkpoint_insts = Param.Bool(True, 140 "enable checkpoint pseudo instructions") 141 do_statistics_insts = Param.Bool(True, 142 "enable statistics pseudo instructions") 143 144 profile = Param.Latency('0ns', "trace the kernel stack") 145 do_quiesce = Param.Bool(True, "enable quiesce instructions") 146 147 workload = VectorParam.Process([], "processes to run") 148 149 if buildEnv['TARGET_ISA'] == 'sparc': 150 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 151 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 152 interrupts = Param.SparcInterrupts( 153 NULL, "Interrupt Controller") 154 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 155 elif buildEnv['TARGET_ISA'] == 'alpha': 156 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 157 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 158 interrupts = Param.AlphaInterrupts( 159 NULL, "Interrupt Controller") 160 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 161 elif buildEnv['TARGET_ISA'] == 'x86': 162 dtb = Param.X86TLB(X86TLB(), "Data TLB") 163 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 164 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 165 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 166 elif buildEnv['TARGET_ISA'] == 'mips': 167 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 168 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 169 interrupts = Param.MipsInterrupts( 170 NULL, "Interrupt Controller") 171 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 172 elif buildEnv['TARGET_ISA'] == 'arm': 173 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 174 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 175 interrupts = Param.ArmInterrupts( 176 NULL, "Interrupt Controller") 177 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 178 elif buildEnv['TARGET_ISA'] == 'power': 179 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 180 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 181 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 182 interrupts = Param.PowerInterrupts( 183 NULL, "Interrupt Controller") 184 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 185 else: 186 print "Don't know what TLB to use for ISA %s" % \ 187 buildEnv['TARGET_ISA'] 188 sys.exit(1) 189 190 max_insts_all_threads = Param.Counter(0, 191 "terminate when all threads have reached this inst count") 192 max_insts_any_thread = Param.Counter(0, 193 "terminate when any thread reaches this inst count") 194 simpoint_start_insts = VectorParam.Counter([], 195 "starting instruction counts of simpoints") 196 max_loads_all_threads = Param.Counter(0, 197 "terminate when all threads have reached this load count") 198 max_loads_any_thread = Param.Counter(0, 199 "terminate when any thread reaches this load count") 200 progress_interval = Param.Frequency('0Hz', 201 "frequency to print out the progress message") 202 203 switched_out = Param.Bool(False, 204 "Leave the CPU switched out after startup (used when switching " \ 205 "between CPU models)") 206 207 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 208 209 icache_port = MasterPort("Instruction Port") 210 dcache_port = MasterPort("Data Port") 211 _cached_ports = ['icache_port', 'dcache_port'] 212 213 branchPred = Param.BranchPredictor(NULL, "Branch Predictor") 214 215 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 216 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 217 218 _uncached_slave_ports = [] 219 _uncached_master_ports = [] 220 if buildEnv['TARGET_ISA'] == 'x86': 221 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 222 _uncached_master_ports += ["interrupts.int_master"] 223 224 def createInterruptController(self): 225 if buildEnv['TARGET_ISA'] == 'sparc': 226 self.interrupts = SparcInterrupts() 227 elif buildEnv['TARGET_ISA'] == 'alpha': 228 self.interrupts = AlphaInterrupts() 229 elif buildEnv['TARGET_ISA'] == 'x86': 230 self.apic_clk_domain = DerivedClockDomain(clk_domain = 231 Parent.clk_domain, 232 clk_divider = 16) 233 self.interrupts = X86LocalApic(clk_domain = self.apic_clk_domain, 234 pio_addr=0x2000000000000000) 235 _localApic = self.interrupts 236 elif buildEnv['TARGET_ISA'] == 'mips': 237 self.interrupts = MipsInterrupts() 238 elif buildEnv['TARGET_ISA'] == 'arm': 239 self.interrupts = ArmInterrupts() 240 elif buildEnv['TARGET_ISA'] == 'power': 241 self.interrupts = PowerInterrupts() 242 else: 243 print "Don't know what Interrupt Controller to use for ISA %s" % \ 244 buildEnv['TARGET_ISA'] 245 sys.exit(1) 246 247 def connectCachedPorts(self, bus): 248 for p in self._cached_ports: 249 exec('self.%s = bus.slave' % p) 250 251 def connectUncachedPorts(self, bus): 252 for p in self._uncached_slave_ports: 253 exec('self.%s = bus.master' % p) 254 for p in self._uncached_master_ports: 255 exec('self.%s = bus.slave' % p) 256 257 def connectAllPorts(self, cached_bus, uncached_bus = None): 258 self.connectCachedPorts(cached_bus) 259 if not uncached_bus: 260 uncached_bus = cached_bus 261 self.connectUncachedPorts(uncached_bus) 262 263 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 264 self.icache = ic 265 self.dcache = dc 266 self.icache_port = ic.cpu_side 267 self.dcache_port = dc.cpu_side 268 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 269 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 270 if iwc and dwc: 271 self.itb_walker_cache = iwc 272 self.dtb_walker_cache = dwc 273 self.itb.walker.port = iwc.cpu_side 274 self.dtb.walker.port = dwc.cpu_side 275 self._cached_ports += ["itb_walker_cache.mem_side", \ 276 "dtb_walker_cache.mem_side"] 277 else: 278 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 279 280 # Checker doesn't need its own tlb caches because it does 281 # functional accesses only 282 if self.checker != NULL: 283 self._cached_ports += ["checker.itb.walker.port", \ 284 "checker.dtb.walker.port"] 285 286 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 287 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 288 # Set a width of 32 bytes (256-bits), which is four times that 289 # of the default bus. The clock of the CPU is inherited by 290 # default. 291 self.toL2Bus = CoherentBus(width = 32) 292 self.connectCachedPorts(self.toL2Bus) 293 self.l2cache = l2c 294 self.toL2Bus.master = self.l2cache.cpu_side 295 self._cached_ports = ['l2cache.mem_side'] 296 297 def createThreads(self): 298 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 299 if self.checker != NULL: 300 self.checker.createThreads() 301 302 def addCheckerCpu(self): 303 pass 304