BaseCPU.py revision 9544:1a075d9bc1bc 
1# Copyright (c) 2012 ARM Limited
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13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
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39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from BranchPredictor import BranchPredictor
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59    from AlphaTLB import AlphaDTB, AlphaITB
60    from AlphaInterrupts import AlphaInterrupts
61    from AlphaISA import AlphaISA
62    isa_class = AlphaISA
63elif buildEnv['TARGET_ISA'] == 'sparc':
64    from SparcTLB import SparcTLB
65    from SparcInterrupts import SparcInterrupts
66    from SparcISA import SparcISA
67    isa_class = SparcISA
68elif buildEnv['TARGET_ISA'] == 'x86':
69    from X86TLB import X86TLB
70    from X86LocalApic import X86LocalApic
71    from X86ISA import X86ISA
72    isa_class = X86ISA
73elif buildEnv['TARGET_ISA'] == 'mips':
74    from MipsTLB import MipsTLB
75    from MipsInterrupts import MipsInterrupts
76    from MipsISA import MipsISA
77    isa_class = MipsISA
78elif buildEnv['TARGET_ISA'] == 'arm':
79    from ArmTLB import ArmTLB
80    from ArmInterrupts import ArmInterrupts
81    from ArmISA import ArmISA
82    isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84    from PowerTLB import PowerTLB
85    from PowerInterrupts import PowerInterrupts
86    from PowerISA import PowerISA
87    isa_class = PowerISA
88
89class BaseCPU(MemObject):
90    type = 'BaseCPU'
91    abstract = True
92    cxx_header = "cpu/base.hh"
93
94    @classmethod
95    def export_methods(cls, code):
96        code('''
97    void switchOut();
98    void takeOverFrom(BaseCPU *cpu);
99    bool switchedOut();
100    void flushTLBs();
101''')
102
103    @classmethod
104    def memory_mode(cls):
105        """Which memory mode does this CPU require?"""
106        return 'invalid'
107
108    @classmethod
109    def require_caches(cls):
110        """Does the CPU model require caches?
111
112        Some CPU models might make assumptions that require them to
113        have caches.
114        """
115        return False
116
117    @classmethod
118    def support_take_over(cls):
119        """Does the CPU model support CPU takeOverFrom?"""
120        return False
121
122    def takeOverFrom(self, old_cpu):
123        self._ccObject.takeOverFrom(old_cpu._ccObject)
124
125
126    system = Param.System(Parent.any, "system object")
127    cpu_id = Param.Int(-1, "CPU identifier")
128    numThreads = Param.Unsigned(1, "number of HW thread contexts")
129
130    function_trace = Param.Bool(False, "Enable function trace")
131    function_trace_start = Param.Tick(0, "Tick to start function trace")
132
133    checker = Param.BaseCPU(NULL, "checker CPU")
134
135    do_checkpoint_insts = Param.Bool(True,
136        "enable checkpoint pseudo instructions")
137    do_statistics_insts = Param.Bool(True,
138        "enable statistics pseudo instructions")
139
140    profile = Param.Latency('0ns', "trace the kernel stack")
141    do_quiesce = Param.Bool(True, "enable quiesce instructions")
142
143    workload = VectorParam.Process([], "processes to run")
144
145    if buildEnv['TARGET_ISA'] == 'sparc':
146        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
147        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
148        interrupts = Param.SparcInterrupts(
149                NULL, "Interrupt Controller")
150        isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
151    elif buildEnv['TARGET_ISA'] == 'alpha':
152        dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
153        itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
154        interrupts = Param.AlphaInterrupts(
155                NULL, "Interrupt Controller")
156        isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
157    elif buildEnv['TARGET_ISA'] == 'x86':
158        dtb = Param.X86TLB(X86TLB(), "Data TLB")
159        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
160        interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
161        isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
162    elif buildEnv['TARGET_ISA'] == 'mips':
163        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
164        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
165        interrupts = Param.MipsInterrupts(
166                NULL, "Interrupt Controller")
167        isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
168    elif buildEnv['TARGET_ISA'] == 'arm':
169        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
170        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
171        interrupts = Param.ArmInterrupts(
172                NULL, "Interrupt Controller")
173        isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
174    elif buildEnv['TARGET_ISA'] == 'power':
175        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
176        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
177        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
178        interrupts = Param.PowerInterrupts(
179                NULL, "Interrupt Controller")
180        isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
181    else:
182        print "Don't know what TLB to use for ISA %s" % \
183            buildEnv['TARGET_ISA']
184        sys.exit(1)
185
186    max_insts_all_threads = Param.Counter(0,
187        "terminate when all threads have reached this inst count")
188    max_insts_any_thread = Param.Counter(0,
189        "terminate when any thread reaches this inst count")
190    max_loads_all_threads = Param.Counter(0,
191        "terminate when all threads have reached this load count")
192    max_loads_any_thread = Param.Counter(0,
193        "terminate when any thread reaches this load count")
194    progress_interval = Param.Frequency('0Hz',
195        "frequency to print out the progress message")
196
197    switched_out = Param.Bool(False,
198        "Leave the CPU switched out after startup (used when switching " \
199        "between CPU models)")
200
201    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
202
203    icache_port = MasterPort("Instruction Port")
204    dcache_port = MasterPort("Data Port")
205    _cached_ports = ['icache_port', 'dcache_port']
206
207    branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
208
209    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
210        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
211
212    _uncached_slave_ports = []
213    _uncached_master_ports = []
214    if buildEnv['TARGET_ISA'] == 'x86':
215        _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
216        _uncached_master_ports += ["interrupts.int_master"]
217
218    def createInterruptController(self):
219        if buildEnv['TARGET_ISA'] == 'sparc':
220            self.interrupts = SparcInterrupts()
221        elif buildEnv['TARGET_ISA'] == 'alpha':
222            self.interrupts = AlphaInterrupts()
223        elif buildEnv['TARGET_ISA'] == 'x86':
224            self.interrupts = X86LocalApic(clock = Parent.clock * 16,
225                                           pio_addr=0x2000000000000000)
226            _localApic = self.interrupts
227        elif buildEnv['TARGET_ISA'] == 'mips':
228            self.interrupts = MipsInterrupts()
229        elif buildEnv['TARGET_ISA'] == 'arm':
230            self.interrupts = ArmInterrupts()
231        elif buildEnv['TARGET_ISA'] == 'power':
232            self.interrupts = PowerInterrupts()
233        else:
234            print "Don't know what Interrupt Controller to use for ISA %s" % \
235                buildEnv['TARGET_ISA']
236            sys.exit(1)
237
238    def connectCachedPorts(self, bus):
239        for p in self._cached_ports:
240            exec('self.%s = bus.slave' % p)
241
242    def connectUncachedPorts(self, bus):
243        for p in self._uncached_slave_ports:
244            exec('self.%s = bus.master' % p)
245        for p in self._uncached_master_ports:
246            exec('self.%s = bus.slave' % p)
247
248    def connectAllPorts(self, cached_bus, uncached_bus = None):
249        self.connectCachedPorts(cached_bus)
250        if not uncached_bus:
251            uncached_bus = cached_bus
252        self.connectUncachedPorts(uncached_bus)
253
254    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
255        self.icache = ic
256        self.dcache = dc
257        self.icache_port = ic.cpu_side
258        self.dcache_port = dc.cpu_side
259        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
260        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
261            if iwc and dwc:
262                self.itb_walker_cache = iwc
263                self.dtb_walker_cache = dwc
264                self.itb.walker.port = iwc.cpu_side
265                self.dtb.walker.port = dwc.cpu_side
266                self._cached_ports += ["itb_walker_cache.mem_side", \
267                                       "dtb_walker_cache.mem_side"]
268            else:
269                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
270
271            # Checker doesn't need its own tlb caches because it does
272            # functional accesses only
273            if self.checker != NULL:
274                self._cached_ports += ["checker.itb.walker.port", \
275                                       "checker.dtb.walker.port"]
276
277    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
278        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
279        # Override the default bus clock of 1 GHz and uses the CPU
280        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
281        # (256-bits), which is four times that of the default bus.
282        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
283        self.connectCachedPorts(self.toL2Bus)
284        self.l2cache = l2c
285        self.toL2Bus.master = self.l2cache.cpu_side
286        self._cached_ports = ['l2cache.mem_side']
287
288    def createThreads(self):
289        self.isa = [ isa_class() for i in xrange(self.numThreads) ]
290        if self.checker != NULL:
291            self.checker.createThreads()
292
293    def addCheckerCpu(self):
294        pass
295