BaseCPU.py revision 9480:d059f8a95a42
13520Sgblack@eecs.umich.edu# Copyright (c) 2012 ARM Limited 23520Sgblack@eecs.umich.edu# All rights reserved. 33520Sgblack@eecs.umich.edu# 43520Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 53520Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 63520Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 73520Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 83520Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 93520Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 103520Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 113520Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 123520Sgblack@eecs.umich.edu# 133520Sgblack@eecs.umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 143520Sgblack@eecs.umich.edu# Copyright (c) 2011 Regents of the University of California 153520Sgblack@eecs.umich.edu# All rights reserved. 163520Sgblack@eecs.umich.edu# 173520Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183520Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 193520Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203520Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213520Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223520Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233520Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243520Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253520Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263520Sgblack@eecs.umich.edu# this software without specific prior written permission. 273520Sgblack@eecs.umich.edu# 283520Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293520Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303520Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313520Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323520Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333520Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343520Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353520Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363520Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374103Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383520Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393520Sgblack@eecs.umich.edu# 405565Snate@binkert.org# Authors: Nathan Binkert 415565Snate@binkert.org# Rick Strong 425565Snate@binkert.org# Andreas Hansson 433520Sgblack@eecs.umich.edu 445565Snate@binkert.orgimport sys 455565Snate@binkert.org 465565Snate@binkert.orgfrom m5.defines import buildEnv 475565Snate@binkert.orgfrom m5.params import * 485565Snate@binkert.orgfrom m5.proxy import * 495565Snate@binkert.org 505565Snate@binkert.orgfrom Bus import CoherentBus 515565Snate@binkert.orgfrom InstTracer import InstTracer 525565Snate@binkert.orgfrom ExeTracer import ExeTracer 535565Snate@binkert.orgfrom MemObject import MemObject 545565Snate@binkert.orgfrom BranchPredictor import BranchPredictor 553520Sgblack@eecs.umich.edu 565565Snate@binkert.orgdefault_tracer = ExeTracer() 575565Snate@binkert.org 585565Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 595565Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 603520Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 615565Snate@binkert.org from AlphaISA import AlphaISA 625565Snate@binkert.org isa_class = AlphaISA 635565Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 645565Snate@binkert.org from SparcTLB import SparcTLB 653520Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 665565Snate@binkert.org from SparcISA import SparcISA 675565Snate@binkert.org isa_class = SparcISA 683520Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 695565Snate@binkert.org from X86TLB import X86TLB 705565Snate@binkert.org from X86LocalApic import X86LocalApic 713520Sgblack@eecs.umich.edu from X86ISA import X86ISA 725565Snate@binkert.org isa_class = X86ISA 735565Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 745565Snate@binkert.org from MipsTLB import MipsTLB 753520Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 765565Snate@binkert.org from MipsISA import MipsISA 775565Snate@binkert.org isa_class = MipsISA 785565Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 795565Snate@binkert.org from ArmTLB import ArmTLB 803520Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 815565Snate@binkert.org from ArmISA import ArmISA 825565Snate@binkert.org isa_class = ArmISA 833520Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'power': 845565Snate@binkert.org from PowerTLB import PowerTLB 855565Snate@binkert.org from PowerInterrupts import PowerInterrupts 863520Sgblack@eecs.umich.edu from PowerISA import PowerISA 875565Snate@binkert.org isa_class = PowerISA 885565Snate@binkert.org 895565Snate@binkert.orgclass BaseCPU(MemObject): 905565Snate@binkert.org type = 'BaseCPU' 913520Sgblack@eecs.umich.edu abstract = True 925565Snate@binkert.org cxx_header = "cpu/base.hh" 935565Snate@binkert.org 945565Snate@binkert.org @classmethod 955565Snate@binkert.org def export_methods(cls, code): 963520Sgblack@eecs.umich.edu code(''' 975565Snate@binkert.org void switchOut(); 985565Snate@binkert.org void takeOverFrom(BaseCPU *cpu); 995565Snate@binkert.org bool switchedOut(); 1003520Sgblack@eecs.umich.edu void flushTLBs(); 1015565Snate@binkert.org''') 1025565Snate@binkert.org 1035565Snate@binkert.org def takeOverFrom(self, old_cpu): 1045565Snate@binkert.org self._ccObject.takeOverFrom(old_cpu._ccObject) 1055565Snate@binkert.org 1065565Snate@binkert.org 1073520Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system object") 1085565Snate@binkert.org cpu_id = Param.Int(-1, "CPU identifier") 1095565Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 1105565Snate@binkert.org 1115565Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1125565Snate@binkert.org function_trace_start = Param.Tick(0, "Tick to start function trace") 1135565Snate@binkert.org 1143520Sgblack@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1155565Snate@binkert.org 1165565Snate@binkert.org do_checkpoint_insts = Param.Bool(True, 1175565Snate@binkert.org "enable checkpoint pseudo instructions") 1185565Snate@binkert.org do_statistics_insts = Param.Bool(True, 1195565Snate@binkert.org "enable statistics pseudo instructions") 1203520Sgblack@eecs.umich.edu 1215565Snate@binkert.org profile = Param.Latency('0ns', "trace the kernel stack") 1225565Snate@binkert.org do_quiesce = Param.Bool(True, "enable quiesce instructions") 1235565Snate@binkert.org 1245565Snate@binkert.org workload = VectorParam.Process([], "processes to run") 1255565Snate@binkert.org 1263521Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 1275565Snate@binkert.org dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1285565Snate@binkert.org itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1293520Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 1305565Snate@binkert.org NULL, "Interrupt Controller") 1315565Snate@binkert.org isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 1325565Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1335565Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1345565Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1355565Snate@binkert.org interrupts = Param.AlphaInterrupts( 1365565Snate@binkert.org NULL, "Interrupt Controller") 1373520Sgblack@eecs.umich.edu isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 1383520Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1393520Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1403520Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1415565Snate@binkert.org interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 1425565Snate@binkert.org isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 1435565Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1445565Snate@binkert.org dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1455565Snate@binkert.org itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1465565Snate@binkert.org interrupts = Param.MipsInterrupts( 1475565Snate@binkert.org NULL, "Interrupt Controller") 1485565Snate@binkert.org isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 1495565Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1505565Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1513633Sktlim@umich.edu itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1523633Sktlim@umich.edu interrupts = Param.ArmInterrupts( 1535565Snate@binkert.org NULL, "Interrupt Controller") 1545565Snate@binkert.org isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 1555565Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'power': 1565565Snate@binkert.org UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1575565Snate@binkert.org dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1585565Snate@binkert.org itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1595565Snate@binkert.org interrupts = Param.PowerInterrupts( 1605565Snate@binkert.org NULL, "Interrupt Controller") 1615565Snate@binkert.org isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 1625565Snate@binkert.org else: 1634103Ssaidi@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1645565Snate@binkert.org buildEnv['TARGET_ISA'] 1654103Ssaidi@eecs.umich.edu sys.exit(1) 1665565Snate@binkert.org 1675565Snate@binkert.org max_insts_all_threads = Param.Counter(0, 1685565Snate@binkert.org "terminate when all threads have reached this inst count") 1695565Snate@binkert.org max_insts_any_thread = Param.Counter(0, 1705565Snate@binkert.org "terminate when any thread reaches this inst count") 1715565Snate@binkert.org max_loads_all_threads = Param.Counter(0, 1725565Snate@binkert.org "terminate when all threads have reached this load count") 1735565Snate@binkert.org max_loads_any_thread = Param.Counter(0, 1743520Sgblack@eecs.umich.edu "terminate when any thread reaches this load count") 1755565Snate@binkert.org progress_interval = Param.Frequency('0Hz', 1765565Snate@binkert.org "frequency to print out the progress message") 1775565Snate@binkert.org 1785565Snate@binkert.org switched_out = Param.Bool(False, 1795565Snate@binkert.org "Leave the CPU switched out after startup (used when switching " \ 1805565Snate@binkert.org "between CPU models)") 1815565Snate@binkert.org 1823520Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1835565Snate@binkert.org 1845565Snate@binkert.org icache_port = MasterPort("Instruction Port") 1855565Snate@binkert.org dcache_port = MasterPort("Data Port") 1865565Snate@binkert.org _cached_ports = ['icache_port', 'dcache_port'] 187 188 branchPred = Param.BranchPredictor(NULL, "Branch Predictor") 189 190 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 191 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 192 193 _uncached_slave_ports = [] 194 _uncached_master_ports = [] 195 if buildEnv['TARGET_ISA'] == 'x86': 196 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 197 _uncached_master_ports += ["interrupts.int_master"] 198 199 def createInterruptController(self): 200 if buildEnv['TARGET_ISA'] == 'sparc': 201 self.interrupts = SparcInterrupts() 202 elif buildEnv['TARGET_ISA'] == 'alpha': 203 self.interrupts = AlphaInterrupts() 204 elif buildEnv['TARGET_ISA'] == 'x86': 205 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 206 self.interrupts = _localApic 207 elif buildEnv['TARGET_ISA'] == 'mips': 208 self.interrupts = MipsInterrupts() 209 elif buildEnv['TARGET_ISA'] == 'arm': 210 self.interrupts = ArmInterrupts() 211 elif buildEnv['TARGET_ISA'] == 'power': 212 self.interrupts = PowerInterrupts() 213 else: 214 print "Don't know what Interrupt Controller to use for ISA %s" % \ 215 buildEnv['TARGET_ISA'] 216 sys.exit(1) 217 218 def connectCachedPorts(self, bus): 219 for p in self._cached_ports: 220 exec('self.%s = bus.slave' % p) 221 222 def connectUncachedPorts(self, bus): 223 for p in self._uncached_slave_ports: 224 exec('self.%s = bus.master' % p) 225 for p in self._uncached_master_ports: 226 exec('self.%s = bus.slave' % p) 227 228 def connectAllPorts(self, cached_bus, uncached_bus = None): 229 self.connectCachedPorts(cached_bus) 230 if not uncached_bus: 231 uncached_bus = cached_bus 232 self.connectUncachedPorts(uncached_bus) 233 234 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 235 self.icache = ic 236 self.dcache = dc 237 self.icache_port = ic.cpu_side 238 self.dcache_port = dc.cpu_side 239 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 240 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 241 if iwc and dwc: 242 self.itb_walker_cache = iwc 243 self.dtb_walker_cache = dwc 244 self.itb.walker.port = iwc.cpu_side 245 self.dtb.walker.port = dwc.cpu_side 246 self._cached_ports += ["itb_walker_cache.mem_side", \ 247 "dtb_walker_cache.mem_side"] 248 else: 249 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 250 251 # Checker doesn't need its own tlb caches because it does 252 # functional accesses only 253 if self.checker != NULL: 254 self._cached_ports += ["checker.itb.walker.port", \ 255 "checker.dtb.walker.port"] 256 257 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 258 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 259 # Override the default bus clock of 1 GHz and uses the CPU 260 # clock for the L1-to-L2 bus, and also set a width of 32 bytes 261 # (256-bits), which is four times that of the default bus. 262 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) 263 self.connectCachedPorts(self.toL2Bus) 264 self.l2cache = l2c 265 self.toL2Bus.master = self.l2cache.cpu_side 266 self._cached_ports = ['l2cache.mem_side'] 267 268 def createThreads(self): 269 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 270 if self.checker != NULL: 271 self.checker.createThreads() 272 273 def addCheckerCpu(self): 274 pass 275