BaseCPU.py revision 9480 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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8# licensed hereunder.  You may use the software subject to the license
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11# modified or unmodified, in source code or in binary form.
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13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
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18# modification, are permitted provided that the following conditions are
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28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from BranchPredictor import BranchPredictor
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59    from AlphaTLB import AlphaDTB, AlphaITB
60    from AlphaInterrupts import AlphaInterrupts
61    from AlphaISA import AlphaISA
62    isa_class = AlphaISA
63elif buildEnv['TARGET_ISA'] == 'sparc':
64    from SparcTLB import SparcTLB
65    from SparcInterrupts import SparcInterrupts
66    from SparcISA import SparcISA
67    isa_class = SparcISA
68elif buildEnv['TARGET_ISA'] == 'x86':
69    from X86TLB import X86TLB
70    from X86LocalApic import X86LocalApic
71    from X86ISA import X86ISA
72    isa_class = X86ISA
73elif buildEnv['TARGET_ISA'] == 'mips':
74    from MipsTLB import MipsTLB
75    from MipsInterrupts import MipsInterrupts
76    from MipsISA import MipsISA
77    isa_class = MipsISA
78elif buildEnv['TARGET_ISA'] == 'arm':
79    from ArmTLB import ArmTLB
80    from ArmInterrupts import ArmInterrupts
81    from ArmISA import ArmISA
82    isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84    from PowerTLB import PowerTLB
85    from PowerInterrupts import PowerInterrupts
86    from PowerISA import PowerISA
87    isa_class = PowerISA
88
89class BaseCPU(MemObject):
90    type = 'BaseCPU'
91    abstract = True
92    cxx_header = "cpu/base.hh"
93
94    @classmethod
95    def export_methods(cls, code):
96        code('''
97    void switchOut();
98    void takeOverFrom(BaseCPU *cpu);
99    bool switchedOut();
100    void flushTLBs();
101''')
102
103    def takeOverFrom(self, old_cpu):
104        self._ccObject.takeOverFrom(old_cpu._ccObject)
105
106
107    system = Param.System(Parent.any, "system object")
108    cpu_id = Param.Int(-1, "CPU identifier")
109    numThreads = Param.Unsigned(1, "number of HW thread contexts")
110
111    function_trace = Param.Bool(False, "Enable function trace")
112    function_trace_start = Param.Tick(0, "Tick to start function trace")
113
114    checker = Param.BaseCPU(NULL, "checker CPU")
115
116    do_checkpoint_insts = Param.Bool(True,
117        "enable checkpoint pseudo instructions")
118    do_statistics_insts = Param.Bool(True,
119        "enable statistics pseudo instructions")
120
121    profile = Param.Latency('0ns', "trace the kernel stack")
122    do_quiesce = Param.Bool(True, "enable quiesce instructions")
123
124    workload = VectorParam.Process([], "processes to run")
125
126    if buildEnv['TARGET_ISA'] == 'sparc':
127        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
128        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
129        interrupts = Param.SparcInterrupts(
130                NULL, "Interrupt Controller")
131        isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
132    elif buildEnv['TARGET_ISA'] == 'alpha':
133        dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
134        itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
135        interrupts = Param.AlphaInterrupts(
136                NULL, "Interrupt Controller")
137        isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
138    elif buildEnv['TARGET_ISA'] == 'x86':
139        dtb = Param.X86TLB(X86TLB(), "Data TLB")
140        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
141        interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
142        isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
143    elif buildEnv['TARGET_ISA'] == 'mips':
144        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
145        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
146        interrupts = Param.MipsInterrupts(
147                NULL, "Interrupt Controller")
148        isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
149    elif buildEnv['TARGET_ISA'] == 'arm':
150        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
151        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
152        interrupts = Param.ArmInterrupts(
153                NULL, "Interrupt Controller")
154        isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
155    elif buildEnv['TARGET_ISA'] == 'power':
156        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
157        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
158        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
159        interrupts = Param.PowerInterrupts(
160                NULL, "Interrupt Controller")
161        isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
162    else:
163        print "Don't know what TLB to use for ISA %s" % \
164            buildEnv['TARGET_ISA']
165        sys.exit(1)
166
167    max_insts_all_threads = Param.Counter(0,
168        "terminate when all threads have reached this inst count")
169    max_insts_any_thread = Param.Counter(0,
170        "terminate when any thread reaches this inst count")
171    max_loads_all_threads = Param.Counter(0,
172        "terminate when all threads have reached this load count")
173    max_loads_any_thread = Param.Counter(0,
174        "terminate when any thread reaches this load count")
175    progress_interval = Param.Frequency('0Hz',
176        "frequency to print out the progress message")
177
178    switched_out = Param.Bool(False,
179        "Leave the CPU switched out after startup (used when switching " \
180        "between CPU models)")
181
182    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
183
184    icache_port = MasterPort("Instruction Port")
185    dcache_port = MasterPort("Data Port")
186    _cached_ports = ['icache_port', 'dcache_port']
187
188    branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
189
190    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
191        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
192
193    _uncached_slave_ports = []
194    _uncached_master_ports = []
195    if buildEnv['TARGET_ISA'] == 'x86':
196        _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
197        _uncached_master_ports += ["interrupts.int_master"]
198
199    def createInterruptController(self):
200        if buildEnv['TARGET_ISA'] == 'sparc':
201            self.interrupts = SparcInterrupts()
202        elif buildEnv['TARGET_ISA'] == 'alpha':
203            self.interrupts = AlphaInterrupts()
204        elif buildEnv['TARGET_ISA'] == 'x86':
205            _localApic = X86LocalApic(pio_addr=0x2000000000000000)
206            self.interrupts = _localApic
207        elif buildEnv['TARGET_ISA'] == 'mips':
208            self.interrupts = MipsInterrupts()
209        elif buildEnv['TARGET_ISA'] == 'arm':
210            self.interrupts = ArmInterrupts()
211        elif buildEnv['TARGET_ISA'] == 'power':
212            self.interrupts = PowerInterrupts()
213        else:
214            print "Don't know what Interrupt Controller to use for ISA %s" % \
215                buildEnv['TARGET_ISA']
216            sys.exit(1)
217
218    def connectCachedPorts(self, bus):
219        for p in self._cached_ports:
220            exec('self.%s = bus.slave' % p)
221
222    def connectUncachedPorts(self, bus):
223        for p in self._uncached_slave_ports:
224            exec('self.%s = bus.master' % p)
225        for p in self._uncached_master_ports:
226            exec('self.%s = bus.slave' % p)
227
228    def connectAllPorts(self, cached_bus, uncached_bus = None):
229        self.connectCachedPorts(cached_bus)
230        if not uncached_bus:
231            uncached_bus = cached_bus
232        self.connectUncachedPorts(uncached_bus)
233
234    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
235        self.icache = ic
236        self.dcache = dc
237        self.icache_port = ic.cpu_side
238        self.dcache_port = dc.cpu_side
239        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
240        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
241            if iwc and dwc:
242                self.itb_walker_cache = iwc
243                self.dtb_walker_cache = dwc
244                self.itb.walker.port = iwc.cpu_side
245                self.dtb.walker.port = dwc.cpu_side
246                self._cached_ports += ["itb_walker_cache.mem_side", \
247                                       "dtb_walker_cache.mem_side"]
248            else:
249                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
250
251            # Checker doesn't need its own tlb caches because it does
252            # functional accesses only
253            if self.checker != NULL:
254                self._cached_ports += ["checker.itb.walker.port", \
255                                       "checker.dtb.walker.port"]
256
257    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
258        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
259        # Override the default bus clock of 1 GHz and uses the CPU
260        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
261        # (256-bits), which is four times that of the default bus.
262        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
263        self.connectCachedPorts(self.toL2Bus)
264        self.l2cache = l2c
265        self.toL2Bus.master = self.l2cache.cpu_side
266        self._cached_ports = ['l2cache.mem_side']
267
268    def createThreads(self):
269        self.isa = [ isa_class() for i in xrange(self.numThreads) ]
270        if self.checker != NULL:
271            self.checker.createThreads()
272
273    def addCheckerCpu(self):
274        pass
275