BaseCPU.py revision 6023
1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from MemObject import MemObject 30from m5.params import * 31from m5.proxy import * 32from m5 import build_env 33from Bus import Bus 34from InstTracer import InstTracer 35from ExeTracer import ExeTracer 36import sys 37 38default_tracer = ExeTracer() 39 40if build_env['TARGET_ISA'] == 'alpha': 41 from AlphaTLB import AlphaDTB, AlphaITB 42 if build_env['FULL_SYSTEM']: 43 from AlphaInterrupts import AlphaInterrupts 44elif build_env['TARGET_ISA'] == 'sparc': 45 from SparcTLB import SparcTLB 46 if build_env['FULL_SYSTEM']: 47 from SparcInterrupts import SparcInterrupts 48elif build_env['TARGET_ISA'] == 'x86': 49 from X86TLB import X86TLB 50 if build_env['FULL_SYSTEM']: 51 from X86LocalApic import X86LocalApic 52elif build_env['TARGET_ISA'] == 'mips': 53 from MipsTLB import MipsTLB 54 if build_env['FULL_SYSTEM']: 55 from MipsInterrupts import MipsInterrupts 56elif build_env['TARGET_ISA'] == 'arm': 57 from ArmTLB import ArmDTB 58 if build_env['FULL_SYSTEM']: 59 from ArmInterrupts import ArmInterrupts 60 61class BaseCPU(MemObject): 62 type = 'BaseCPU' 63 abstract = True 64 65 system = Param.System(Parent.any, "system object") 66 cpu_id = Param.Int(-1, "CPU identifier") 67 numThreads = Param.Unsigned(1, "number of HW thread contexts") 68 69 function_trace = Param.Bool(False, "Enable function trace") 70 function_trace_start = Param.Tick(0, "Cycle to start function trace") 71 72 checker = Param.BaseCPU(NULL, "checker CPU") 73 74 do_checkpoint_insts = Param.Bool(True, 75 "enable checkpoint pseudo instructions") 76 do_statistics_insts = Param.Bool(True, 77 "enable statistics pseudo instructions") 78 79 if build_env['FULL_SYSTEM']: 80 profile = Param.Latency('0ns', "trace the kernel stack") 81 do_quiesce = Param.Bool(True, "enable quiesce instructions") 82 else: 83 workload = VectorParam.Process("processes to run") 84 85 if build_env['TARGET_ISA'] == 'sparc': 86 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 87 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 88 if build_env['FULL_SYSTEM']: 89 interrupts = Param.SparcInterrupts( 90 SparcInterrupts(), "Interrupt Controller") 91 elif build_env['TARGET_ISA'] == 'alpha': 92 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 93 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 94 if build_env['FULL_SYSTEM']: 95 interrupts = Param.AlphaInterrupts( 96 AlphaInterrupts(), "Interrupt Controller") 97 elif build_env['TARGET_ISA'] == 'x86': 98 dtb = Param.X86TLB(X86TLB(), "Data TLB") 99 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 100 if build_env['FULL_SYSTEM']: 101 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 102 interrupts = \ 103 Param.X86LocalApic(_localApic, "Interrupt Controller") 104 elif build_env['TARGET_ISA'] == 'mips': 105 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 106 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 107 if build_env['FULL_SYSTEM']: 108 interrupts = Param.MipsInterrupts( 109 MipsInterrupts(), "Interrupt Controller") 110 elif build_env['TARGET_ISA'] == 'arm': 111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 112 dtb = Param.ArmTLB(ArmDTB(), "Data TLB") 113 itb = Param.ArmTLB(ArmITB(), "Instruction TLB") 114 if build_env['FULL_SYSTEM']: 115 interrupts = Param.ArmInterrupts( 116 ArmInterrupts(), "Interrupt Controller") 117 else: 118 print "Don't know what TLB to use for ISA %s" % \ 119 build_env['TARGET_ISA'] 120 sys.exit(1) 121 122 max_insts_all_threads = Param.Counter(0, 123 "terminate when all threads have reached this inst count") 124 max_insts_any_thread = Param.Counter(0, 125 "terminate when any thread reaches this inst count") 126 max_loads_all_threads = Param.Counter(0, 127 "terminate when all threads have reached this load count") 128 max_loads_any_thread = Param.Counter(0, 129 "terminate when any thread reaches this load count") 130 progress_interval = Param.Tick(0, 131 "interval to print out the progress message") 132 133 defer_registration = Param.Bool(False, 134 "defer registration with system (for sampling)") 135 136 clock = Param.Clock('1t', "clock speed") 137 phase = Param.Latency('0ns', "clock phase") 138 139 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 140 141 _mem_ports = [] 142 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 143 _mem_ports = ["itb.walker.port", 144 "dtb.walker.port", 145 "interrupts.pio", 146 "interrupts.int_port"] 147 148 def connectMemPorts(self, bus): 149 for p in self._mem_ports: 150 if p != 'physmem_port': 151 exec('self.%s = bus.port' % p) 152 153 def addPrivateSplitL1Caches(self, ic, dc): 154 assert(len(self._mem_ports) < 6) 155 self.icache = ic 156 self.dcache = dc 157 self.icache_port = ic.cpu_side 158 self.dcache_port = dc.cpu_side 159 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 160 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 161 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 162 163 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 164 self.addPrivateSplitL1Caches(ic, dc) 165 self.toL2Bus = Bus() 166 self.connectMemPorts(self.toL2Bus) 167 self.l2cache = l2c 168 self.l2cache.cpu_side = self.toL2Bus.port 169 self._mem_ports = ['l2cache.mem_side'] 170 171 if build_env['TARGET_ISA'] == 'mips': 172 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 173 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 174 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 175 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 176 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 177 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 178 CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 179 CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 180 CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 181 CP0_Config_AT = Param.Unsigned(0,"No Description") 182 CP0_Config_AR = Param.Unsigned(0,"No Description") 183 CP0_Config_MT = Param.Unsigned(0,"No Description") 184 CP0_Config_VI = Param.Unsigned(0,"No Description") 185 CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 186 CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 187 CP0_Config1_IS = Param.Unsigned(0,"No Description") 188 CP0_Config1_IL = Param.Unsigned(0,"No Description") 189 CP0_Config1_IA = Param.Unsigned(0,"No Description") 190 CP0_Config1_DS = Param.Unsigned(0,"No Description") 191 CP0_Config1_DL = Param.Unsigned(0,"No Description") 192 CP0_Config1_DA = Param.Unsigned(0,"No Description") 193 CP0_Config1_C2 = Param.Bool(False,"No Description") 194 CP0_Config1_MD = Param.Bool(False,"No Description") 195 CP0_Config1_PC = Param.Bool(False,"No Description") 196 CP0_Config1_WR = Param.Bool(False,"No Description") 197 CP0_Config1_CA = Param.Bool(False,"No Description") 198 CP0_Config1_EP = Param.Bool(False,"No Description") 199 CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 200 CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 201 CP0_Config2_TU = Param.Unsigned(0,"No Description") 202 CP0_Config2_TS = Param.Unsigned(0,"No Description") 203 CP0_Config2_TL = Param.Unsigned(0,"No Description") 204 CP0_Config2_TA = Param.Unsigned(0,"No Description") 205 CP0_Config2_SU = Param.Unsigned(0,"No Description") 206 CP0_Config2_SS = Param.Unsigned(0,"No Description") 207 CP0_Config2_SL = Param.Unsigned(0,"No Description") 208 CP0_Config2_SA = Param.Unsigned(0,"No Description") 209 CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 210 CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 211 CP0_Config3_LPA = Param.Bool(False,"No Description") 212 CP0_Config3_VEIC = Param.Bool(False,"No Description") 213 CP0_Config3_VInt = Param.Bool(False,"No Description") 214 CP0_Config3_SP = Param.Bool(False,"No Description") 215 CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 216 CP0_Config3_SM = Param.Bool(False,"No Description") 217 CP0_Config3_TL = Param.Bool(False,"No Description") 218 CP0_WatchHi_M = Param.Bool(False,"No Description") 219 CP0_PerfCtr_M = Param.Bool(False,"No Description") 220 CP0_PerfCtr_W = Param.Bool(False,"No Description") 221 CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 222 CP0_Config = Param.Unsigned(0,"CP0 Config Register") 223 CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 224 CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 225 CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") 226