BaseCPU.py revision 5780:50c9d48de3ca 
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from MemObject import MemObject
30from m5.params import *
31from m5.proxy import *
32from m5 import build_env
33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41    from AlphaTLB import AlphaDTB, AlphaITB
42    if build_env['FULL_SYSTEM']:
43        from AlphaInterrupts import AlphaInterrupts
44elif build_env['TARGET_ISA'] == 'sparc':
45    from SparcTLB import SparcDTB, SparcITB
46    if build_env['FULL_SYSTEM']:
47        from SparcInterrupts import SparcInterrupts
48elif build_env['TARGET_ISA'] == 'x86':
49    from X86TLB import X86DTB, X86ITB
50    if build_env['FULL_SYSTEM']:
51        from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
53    from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
54    if build_env['FULL_SYSTEM']:
55        from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
57    from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
58    if build_env['FULL_SYSTEM']:
59        from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):
62    type = 'BaseCPU'
63    abstract = True
64
65    system = Param.System(Parent.any, "system object")
66    cpu_id = Param.Int(-1, "CPU identifier")
67    numThreads = Param.Unsigned(1, "number of HW thread contexts")
68
69    function_trace = Param.Bool(False, "Enable function trace")
70    function_trace_start = Param.Tick(0, "Cycle to start function trace")
71
72    checker = Param.BaseCPU("checker CPU")
73
74    do_checkpoint_insts = Param.Bool(True,
75        "enable checkpoint pseudo instructions")
76    do_statistics_insts = Param.Bool(True,
77        "enable statistics pseudo instructions")
78
79    if build_env['FULL_SYSTEM']:
80        profile = Param.Latency('0ns', "trace the kernel stack")
81        do_quiesce = Param.Bool(True, "enable quiesce instructions")
82    else:
83        workload = VectorParam.Process("processes to run")
84
85    if build_env['TARGET_ISA'] == 'sparc':
86        dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
87        itb = Param.SparcITB(SparcITB(), "Instruction TLB")
88        if build_env['FULL_SYSTEM']:
89            interrupts = Param.SparcInterrupts(
90                SparcInterrupts(), "Interrupt Controller")
91    elif build_env['TARGET_ISA'] == 'alpha':
92        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
93        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
94        if build_env['FULL_SYSTEM']:
95            interrupts = Param.AlphaInterrupts(
96                AlphaInterrupts(), "Interrupt Controller")
97    elif build_env['TARGET_ISA'] == 'x86':
98        dtb = Param.X86DTB(X86DTB(), "Data TLB")
99        itb = Param.X86ITB(X86ITB(), "Instruction TLB")
100        if build_env['FULL_SYSTEM']:
101            _localApic = X86LocalApic(pio_addr=0x2000000000000000)
102            interrupts = \
103                Param.X86LocalApic(_localApic, "Interrupt Controller")
104    elif build_env['TARGET_ISA'] == 'mips':
105        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
106        dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
107        itb = Param.MipsITB(MipsITB(), "Instruction TLB")
108        tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
109        if build_env['FULL_SYSTEM']:
110            interrupts = Param.MipsInterrupts(
111                    MipsInterrupts(), "Interrupt Controller")
112    elif build_env['TARGET_ISA'] == 'arm':
113        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
114        dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
115        itb = Param.ArmITB(ArmITB(), "Instruction TLB")
116        tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
117        if build_env['FULL_SYSTEM']:
118            interrupts = Param.ArmInterrupts(
119                    ArmInterrupts(), "Interrupt Controller")
120    else:
121        print "Don't know what TLB to use for ISA %s" % \
122            build_env['TARGET_ISA']
123        sys.exit(1)
124
125    max_insts_all_threads = Param.Counter(0,
126        "terminate when all threads have reached this inst count")
127    max_insts_any_thread = Param.Counter(0,
128        "terminate when any thread reaches this inst count")
129    max_loads_all_threads = Param.Counter(0,
130        "terminate when all threads have reached this load count")
131    max_loads_any_thread = Param.Counter(0,
132        "terminate when any thread reaches this load count")
133    progress_interval = Param.Tick(0,
134        "interval to print out the progress message")
135
136    defer_registration = Param.Bool(False,
137        "defer registration with system (for sampling)")
138
139    clock = Param.Clock('1t', "clock speed")
140    phase = Param.Latency('0ns', "clock phase")
141
142    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
143
144    _mem_ports = []
145    if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
146        _mem_ports = ["itb.walker.port",
147                      "dtb.walker.port",
148                      "interrupts.pio",
149                      "interrupts.int_port"]
150
151    def connectMemPorts(self, bus):
152        for p in self._mem_ports:
153            if p != 'physmem_port':
154                exec('self.%s = bus.port' % p)
155
156    def addPrivateSplitL1Caches(self, ic, dc):
157        assert(len(self._mem_ports) < 6)
158        self.icache = ic
159        self.dcache = dc
160        self.icache_port = ic.cpu_side
161        self.dcache_port = dc.cpu_side
162        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
163        if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
164            self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
165
166    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
167        self.addPrivateSplitL1Caches(ic, dc)
168        self.toL2Bus = Bus()
169        self.connectMemPorts(self.toL2Bus)
170        self.l2cache = l2c
171        self.l2cache.cpu_side = self.toL2Bus.port
172        self._mem_ports = ['l2cache.mem_side']
173
174    if build_env['TARGET_ISA'] == 'mips':
175        CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
176        CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
177        CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
178        CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
179        CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
180        CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
181        CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
182        CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
183        CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
184        CP0_Config_AT = Param.Unsigned(0,"No Description")
185        CP0_Config_AR = Param.Unsigned(0,"No Description")
186        CP0_Config_MT = Param.Unsigned(0,"No Description")
187        CP0_Config_VI = Param.Unsigned(0,"No Description")
188        CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
189        CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
190        CP0_Config1_IS = Param.Unsigned(0,"No Description")
191        CP0_Config1_IL = Param.Unsigned(0,"No Description")
192        CP0_Config1_IA = Param.Unsigned(0,"No Description")
193        CP0_Config1_DS = Param.Unsigned(0,"No Description")
194        CP0_Config1_DL = Param.Unsigned(0,"No Description")
195        CP0_Config1_DA = Param.Unsigned(0,"No Description")
196        CP0_Config1_C2 = Param.Bool(False,"No Description")
197        CP0_Config1_MD = Param.Bool(False,"No Description")
198        CP0_Config1_PC = Param.Bool(False,"No Description")
199        CP0_Config1_WR = Param.Bool(False,"No Description")
200        CP0_Config1_CA = Param.Bool(False,"No Description")
201        CP0_Config1_EP = Param.Bool(False,"No Description")
202        CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
203        CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
204        CP0_Config2_TU = Param.Unsigned(0,"No Description")
205        CP0_Config2_TS = Param.Unsigned(0,"No Description")
206        CP0_Config2_TL = Param.Unsigned(0,"No Description")
207        CP0_Config2_TA = Param.Unsigned(0,"No Description")
208        CP0_Config2_SU = Param.Unsigned(0,"No Description")
209        CP0_Config2_SS = Param.Unsigned(0,"No Description")
210        CP0_Config2_SL = Param.Unsigned(0,"No Description")
211        CP0_Config2_SA = Param.Unsigned(0,"No Description")
212        CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
213        CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
214        CP0_Config3_LPA = Param.Bool(False,"No Description")
215        CP0_Config3_VEIC = Param.Bool(False,"No Description")
216        CP0_Config3_VInt = Param.Bool(False,"No Description")
217        CP0_Config3_SP = Param.Bool(False,"No Description")
218        CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
219        CP0_Config3_SM = Param.Bool(False,"No Description")
220        CP0_Config3_TL = Param.Bool(False,"No Description")
221        CP0_WatchHi_M = Param.Bool(False,"No Description")
222        CP0_PerfCtr_M = Param.Bool(False,"No Description")
223        CP0_PerfCtr_W = Param.Bool(False,"No Description")
224        CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
225        CP0_Config = Param.Unsigned(0,"CP0 Config Register")
226        CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
227        CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
228        CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
229