BaseCPU.py revision 5648:e8abda6e0980 
1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from MemObject import MemObject
30from m5.params import *
31from m5.proxy import *
32from m5 import build_env
33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41    from AlphaTLB import AlphaDTB, AlphaITB
42    if build_env['FULL_SYSTEM']:
43        from AlphaInterrupts import AlphaInterrupts
44elif build_env['TARGET_ISA'] == 'sparc':
45    from SparcTLB import SparcDTB, SparcITB
46    if build_env['FULL_SYSTEM']:
47        from SparcInterrupts import SparcInterrupts
48elif build_env['TARGET_ISA'] == 'x86':
49    from X86TLB import X86DTB, X86ITB
50    if build_env['FULL_SYSTEM']:
51        from X86LocalApic import X86LocalApic
52elif build_env['TARGET_ISA'] == 'mips':
53    from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
54    if build_env['FULL_SYSTEM']:
55        from MipsInterrupts import MipsInterrupts
56elif build_env['TARGET_ISA'] == 'arm':
57    from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
58    if build_env['FULL_SYSTEM']:
59        from ArmInterrupts import ArmInterrupts
60
61class BaseCPU(MemObject):
62    type = 'BaseCPU'
63    abstract = True
64
65    system = Param.System(Parent.any, "system object")
66    cpu_id = Param.Int("CPU identifier")
67    numThreads = Param.Unsigned(1, "number of HW thread contexts")
68
69    function_trace = Param.Bool(False, "Enable function trace")
70    function_trace_start = Param.Tick(0, "Cycle to start function trace")
71
72    checker = Param.BaseCPU("checker CPU")
73
74    if build_env['FULL_SYSTEM']:
75        profile = Param.Latency('0ns', "trace the kernel stack")
76        do_quiesce = Param.Bool(True, "enable quiesce instructions")
77        do_checkpoint_insts = Param.Bool(True,
78            "enable checkpoint pseudo instructions")
79        do_statistics_insts = Param.Bool(True,
80            "enable statistics pseudo instructions")
81    else:
82        workload = VectorParam.Process("processes to run")
83
84    if build_env['TARGET_ISA'] == 'sparc':
85        dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
86        itb = Param.SparcITB(SparcITB(), "Instruction TLB")
87        if build_env['FULL_SYSTEM']:
88            interrupts = Param.SparcInterrupts(
89                SparcInterrupts(), "Interrupt Controller")
90    elif build_env['TARGET_ISA'] == 'alpha':
91        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
92        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
93        if build_env['FULL_SYSTEM']:
94            interrupts = Param.AlphaInterrupts(
95                AlphaInterrupts(), "Interrupt Controller")
96    elif build_env['TARGET_ISA'] == 'x86':
97        dtb = Param.X86DTB(X86DTB(), "Data TLB")
98        itb = Param.X86ITB(X86ITB(), "Instruction TLB")
99        if build_env['FULL_SYSTEM']:
100            _localApic = X86LocalApic(pio_addr=0xa000000000000000)
101            interrupts = \
102                Param.X86LocalApic(_localApic, "Interrupt Controller")
103    elif build_env['TARGET_ISA'] == 'mips':
104        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
105        dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
106        itb = Param.MipsITB(MipsITB(), "Instruction TLB")
107        tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
108        if build_env['FULL_SYSTEM']:
109            interrupts = Param.MipsInterrupts(
110                    MipsInterrupts(), "Interrupt Controller")
111    elif build_env['TARGET_ISA'] == 'arm':
112        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
113        dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
114        itb = Param.ArmITB(ArmITB(), "Instruction TLB")
115        tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
116        if build_env['FULL_SYSTEM']:
117            interrupts = Param.ArmInterrupts(
118                    ArmInterrupts(), "Interrupt Controller")
119    else:
120        print "Don't know what TLB to use for ISA %s" % \
121            build_env['TARGET_ISA']
122        sys.exit(1)
123
124    max_insts_all_threads = Param.Counter(0,
125        "terminate when all threads have reached this inst count")
126    max_insts_any_thread = Param.Counter(0,
127        "terminate when any thread reaches this inst count")
128    max_loads_all_threads = Param.Counter(0,
129        "terminate when all threads have reached this load count")
130    max_loads_any_thread = Param.Counter(0,
131        "terminate when any thread reaches this load count")
132    progress_interval = Param.Tick(0,
133        "interval to print out the progress message")
134
135    defer_registration = Param.Bool(False,
136        "defer registration with system (for sampling)")
137
138    clock = Param.Clock('1t', "clock speed")
139    phase = Param.Latency('0ns', "clock phase")
140
141    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
142
143    _mem_ports = []
144    if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
145        _mem_ports = ["itb.walker.port",
146                      "dtb.walker.port",
147                      "interrupts.pio"]
148
149    def connectMemPorts(self, bus):
150        for p in self._mem_ports:
151            if p != 'physmem_port':
152                exec('self.%s = bus.port' % p)
153
154    def addPrivateSplitL1Caches(self, ic, dc):
155        assert(len(self._mem_ports) < 6)
156        self.icache = ic
157        self.dcache = dc
158        self.icache_port = ic.cpu_side
159        self.dcache_port = dc.cpu_side
160        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
161        if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
162            self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
163
164    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
165        self.addPrivateSplitL1Caches(ic, dc)
166        self.toL2Bus = Bus()
167        self.connectMemPorts(self.toL2Bus)
168        self.l2cache = l2c
169        self.l2cache.cpu_side = self.toL2Bus.port
170        self._mem_ports = ['l2cache.mem_side']
171
172    if build_env['TARGET_ISA'] == 'mips':
173        CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
174        CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
175        CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
176        CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
177        CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
178        CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
179        CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
180        CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
181        CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
182        CP0_Config_AT = Param.Unsigned(0,"No Description")
183        CP0_Config_AR = Param.Unsigned(0,"No Description")
184        CP0_Config_MT = Param.Unsigned(0,"No Description")
185        CP0_Config_VI = Param.Unsigned(0,"No Description")
186        CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
187        CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
188        CP0_Config1_IS = Param.Unsigned(0,"No Description")
189        CP0_Config1_IL = Param.Unsigned(0,"No Description")
190        CP0_Config1_IA = Param.Unsigned(0,"No Description")
191        CP0_Config1_DS = Param.Unsigned(0,"No Description")
192        CP0_Config1_DL = Param.Unsigned(0,"No Description")
193        CP0_Config1_DA = Param.Unsigned(0,"No Description")
194        CP0_Config1_C2 = Param.Bool(False,"No Description")
195        CP0_Config1_MD = Param.Bool(False,"No Description")
196        CP0_Config1_PC = Param.Bool(False,"No Description")
197        CP0_Config1_WR = Param.Bool(False,"No Description")
198        CP0_Config1_CA = Param.Bool(False,"No Description")
199        CP0_Config1_EP = Param.Bool(False,"No Description")
200        CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
201        CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
202        CP0_Config2_TU = Param.Unsigned(0,"No Description")
203        CP0_Config2_TS = Param.Unsigned(0,"No Description")
204        CP0_Config2_TL = Param.Unsigned(0,"No Description")
205        CP0_Config2_TA = Param.Unsigned(0,"No Description")
206        CP0_Config2_SU = Param.Unsigned(0,"No Description")
207        CP0_Config2_SS = Param.Unsigned(0,"No Description")
208        CP0_Config2_SL = Param.Unsigned(0,"No Description")
209        CP0_Config2_SA = Param.Unsigned(0,"No Description")
210        CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
211        CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
212        CP0_Config3_LPA = Param.Bool(False,"No Description")
213        CP0_Config3_VEIC = Param.Bool(False,"No Description")
214        CP0_Config3_VInt = Param.Bool(False,"No Description")
215        CP0_Config3_SP = Param.Bool(False,"No Description")
216        CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
217        CP0_Config3_SM = Param.Bool(False,"No Description")
218        CP0_Config3_TL = Param.Bool(False,"No Description")
219        CP0_WatchHi_M = Param.Bool(False,"No Description")
220        CP0_PerfCtr_M = Param.Bool(False,"No Description")
221        CP0_PerfCtr_W = Param.Bool(False,"No Description")
222        CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
223        CP0_Config = Param.Unsigned(0,"CP0 Config Register")
224        CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
225        CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
226        CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
227