BaseCPU.py revision 5335
1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from m5 import build_env 33from Bus import Bus 34from InstTracer import InstTracer 35from ExeTracer import ExeTracer 36import sys 37 38default_tracer = ExeTracer() 39 40if build_env['TARGET_ISA'] == 'alpha': 41 from AlphaTLB import AlphaDTB, AlphaITB 42elif build_env['TARGET_ISA'] == 'sparc': 43 from SparcTLB import SparcDTB, SparcITB 44elif build_env['TARGET_ISA'] == 'x86': 45 from X86TLB import X86DTB, X86ITB 46elif build_env['TARGET_ISA'] == 'mips': 47 from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB 48elif build_env['TARGET_ISA'] == 'arm': 49 from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB 50 51class BaseCPU(SimObject): 52 type = 'BaseCPU' 53 abstract = True 54 55 system = Param.System(Parent.any, "system object") 56 cpu_id = Param.Int("CPU identifier") 57 58 if build_env['FULL_SYSTEM']: 59 do_quiesce = Param.Bool(True, "enable quiesce instructions") 60 do_checkpoint_insts = Param.Bool(True, 61 "enable checkpoint pseudo instructions") 62 do_statistics_insts = Param.Bool(True, 63 "enable statistics pseudo instructions") 64 else: 65 workload = VectorParam.Process("processes to run") 66 67 if build_env['TARGET_ISA'] == 'sparc': 68 dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 69 itb = Param.SparcITB(SparcITB(), "Instruction TLB") 70 elif build_env['TARGET_ISA'] == 'alpha': 71 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 72 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 73 elif build_env['TARGET_ISA'] == 'x86': 74 dtb = Param.X86DTB(X86DTB(), "Data TLB") 75 itb = Param.X86ITB(X86ITB(), "Instruction TLB") 76 elif build_env['TARGET_ISA'] == 'mips': 77 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 78 dtb = Param.MipsDTB(MipsDTB(), "Data TLB") 79 itb = Param.MipsITB(MipsITB(), "Instruction TLB") 80 tlb = Param.MipsUTB(MipsUTB(), "Unified TLB") 81 elif build_env['TARGET_ISA'] == 'arm': 82 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 83 dtb = Param.ArmDTB(ArmDTB(), "Data TLB") 84 itb = Param.ArmITB(ArmITB(), "Instruction TLB") 85 tlb = Param.ArmUTB(ArmUTB(), "Unified TLB") 86 else: 87 print "Don't know what TLB to use for ISA %s" % \ 88 build_env['TARGET_ISA'] 89 sys.exit(1) 90 91 max_insts_all_threads = Param.Counter(0, 92 "terminate when all threads have reached this inst count") 93 max_insts_any_thread = Param.Counter(0, 94 "terminate when any thread reaches this inst count") 95 max_loads_all_threads = Param.Counter(0, 96 "terminate when all threads have reached this load count") 97 max_loads_any_thread = Param.Counter(0, 98 "terminate when any thread reaches this load count") 99 progress_interval = Param.Tick(0, 100 "interval to print out the progress message") 101 102 defer_registration = Param.Bool(False, 103 "defer registration with system (for sampling)") 104 105 clock = Param.Clock('1t', "clock speed") 106 phase = Param.Latency('0ns', "clock phase") 107 108 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 109 110 _mem_ports = [] 111 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 112 _mem_ports = ["itb.walker.port", "dtb.walker.port"] 113 114 def connectMemPorts(self, bus): 115 for p in self._mem_ports: 116 if p != 'physmem_port': 117 exec('self.%s = bus.port' % p) 118 119 def addPrivateSplitL1Caches(self, ic, dc): 120 assert(len(self._mem_ports) < 6) 121 self.icache = ic 122 self.dcache = dc 123 self.icache_port = ic.cpu_side 124 self.dcache_port = dc.cpu_side 125 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 126 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 127 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 128 129 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 130 self.addPrivateSplitL1Caches(ic, dc) 131 self.toL2Bus = Bus() 132 self.connectMemPorts(self.toL2Bus) 133 self.l2cache = l2c 134 self.l2cache.cpu_side = self.toL2Bus.port 135 self._mem_ports = ['l2cache.mem_side'] 136 137 if build_env['TARGET_ISA'] == 'mips': 138 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 139 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 140 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 141 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 142 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 143 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 144 CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 145 CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 146 CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 147 CP0_Config_AT = Param.Unsigned(0,"No Description") 148 CP0_Config_AR = Param.Unsigned(0,"No Description") 149 CP0_Config_MT = Param.Unsigned(0,"No Description") 150 CP0_Config_VI = Param.Unsigned(0,"No Description") 151 CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 152 CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 153 CP0_Config1_IS = Param.Unsigned(0,"No Description") 154 CP0_Config1_IL = Param.Unsigned(0,"No Description") 155 CP0_Config1_IA = Param.Unsigned(0,"No Description") 156 CP0_Config1_DS = Param.Unsigned(0,"No Description") 157 CP0_Config1_DL = Param.Unsigned(0,"No Description") 158 CP0_Config1_DA = Param.Unsigned(0,"No Description") 159 CP0_Config1_C2 = Param.Bool(False,"No Description") 160 CP0_Config1_MD = Param.Bool(False,"No Description") 161 CP0_Config1_PC = Param.Bool(False,"No Description") 162 CP0_Config1_WR = Param.Bool(False,"No Description") 163 CP0_Config1_CA = Param.Bool(False,"No Description") 164 CP0_Config1_EP = Param.Bool(False,"No Description") 165 CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 166 CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 167 CP0_Config2_TU = Param.Unsigned(0,"No Description") 168 CP0_Config2_TS = Param.Unsigned(0,"No Description") 169 CP0_Config2_TL = Param.Unsigned(0,"No Description") 170 CP0_Config2_TA = Param.Unsigned(0,"No Description") 171 CP0_Config2_SU = Param.Unsigned(0,"No Description") 172 CP0_Config2_SS = Param.Unsigned(0,"No Description") 173 CP0_Config2_SL = Param.Unsigned(0,"No Description") 174 CP0_Config2_SA = Param.Unsigned(0,"No Description") 175 CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 176 CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 177 CP0_Config3_LPA = Param.Bool(False,"No Description") 178 CP0_Config3_VEIC = Param.Bool(False,"No Description") 179 CP0_Config3_VInt = Param.Bool(False,"No Description") 180 CP0_Config3_SP = Param.Bool(False,"No Description") 181 CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 182 CP0_Config3_SM = Param.Bool(False,"No Description") 183 CP0_Config3_TL = Param.Bool(False,"No Description") 184 CP0_WatchHi_M = Param.Bool(False,"No Description") 185 CP0_PerfCtr_M = Param.Bool(False,"No Description") 186 CP0_PerfCtr_W = Param.Bool(False,"No Description") 187 CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 188 CP0_Config = Param.Unsigned(0,"CP0 Config Register") 189 CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 190 CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 191 CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") 192