BaseCPU.py revision 5281 
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.SimObject import SimObject
30from m5.params import *
31from m5.proxy import *
32from m5 import build_env
33from Bus import Bus
34from InstTracer import InstTracer
35from ExeTracer import ExeTracer
36import sys
37
38default_tracer = ExeTracer()
39
40if build_env['TARGET_ISA'] == 'alpha':
41    from AlphaTLB import AlphaDTB, AlphaITB
42elif build_env['TARGET_ISA'] == 'sparc':
43    from SparcTLB import SparcDTB, SparcITB
44elif build_env['TARGET_ISA'] == 'x86':
45    from X86TLB import X86DTB, X86ITB
46elif build_env['TARGET_ISA'] == 'mips':
47    from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
48
49class BaseCPU(SimObject):
50    type = 'BaseCPU'
51    abstract = True
52
53    system = Param.System(Parent.any, "system object")
54    cpu_id = Param.Int("CPU identifier")
55
56    if build_env['FULL_SYSTEM']:
57        do_quiesce = Param.Bool(True, "enable quiesce instructions")
58        do_checkpoint_insts = Param.Bool(True,
59            "enable checkpoint pseudo instructions")
60        do_statistics_insts = Param.Bool(True,
61            "enable statistics pseudo instructions")
62    else:
63        workload = VectorParam.Process("processes to run")
64
65    if build_env['TARGET_ISA'] == 'sparc':
66        dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
67        itb = Param.SparcITB(SparcITB(), "Instruction TLB")
68    elif build_env['TARGET_ISA'] == 'alpha':
69        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
70        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
71    elif build_env['TARGET_ISA'] == 'x86':
72        dtb = Param.X86DTB(X86DTB(), "Data TLB")
73        itb = Param.X86ITB(X86ITB(), "Instruction TLB")
74    elif build_env['TARGET_ISA'] == 'mips':
75        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
76        dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
77        itb = Param.MipsITB(MipsITB(), "Instruction TLB")
78        tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
79    else:
80        print "Don't know what TLB to use for ISA %s" % \
81            build_env['TARGET_ISA']
82        sys.exit(1)
83
84    max_insts_all_threads = Param.Counter(0,
85        "terminate when all threads have reached this inst count")
86    max_insts_any_thread = Param.Counter(0,
87        "terminate when any thread reaches this inst count")
88    max_loads_all_threads = Param.Counter(0,
89        "terminate when all threads have reached this load count")
90    max_loads_any_thread = Param.Counter(0,
91        "terminate when any thread reaches this load count")
92    progress_interval = Param.Tick(0,
93        "interval to print out the progress message")
94
95    defer_registration = Param.Bool(False,
96        "defer registration with system (for sampling)")
97
98    clock = Param.Clock('1t', "clock speed")
99    phase = Param.Latency('0ns', "clock phase")
100
101    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
102
103    _mem_ports = []
104    if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
105        _mem_ports = ["itb.walker.port", "dtb.walker.port"]
106
107    def connectMemPorts(self, bus):
108        for p in self._mem_ports:
109            if p != 'physmem_port':
110                exec('self.%s = bus.port' % p)
111
112    def addPrivateSplitL1Caches(self, ic, dc):
113        assert(len(self._mem_ports) < 6)
114        self.icache = ic
115        self.dcache = dc
116        self.icache_port = ic.cpu_side
117        self.dcache_port = dc.cpu_side
118        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
119        if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
120            self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
121
122    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
123        self.addPrivateSplitL1Caches(ic, dc)
124        self.toL2Bus = Bus()
125        self.connectMemPorts(self.toL2Bus)
126        self.l2cache = l2c
127        self.l2cache.cpu_side = self.toL2Bus.port
128        self._mem_ports = ['l2cache.mem_side']
129
130    if build_env['TARGET_ISA'] == 'mips':
131        CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
132        CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
133        CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
134        CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
135        CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
136        CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
137        CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
138        CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
139        CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
140        CP0_Config_AT = Param.Unsigned(0,"No Description")
141        CP0_Config_AR = Param.Unsigned(0,"No Description")
142        CP0_Config_MT = Param.Unsigned(0,"No Description")
143        CP0_Config_VI = Param.Unsigned(0,"No Description")
144        CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
145        CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
146        CP0_Config1_IS = Param.Unsigned(0,"No Description")
147        CP0_Config1_IL = Param.Unsigned(0,"No Description")
148        CP0_Config1_IA = Param.Unsigned(0,"No Description")
149        CP0_Config1_DS = Param.Unsigned(0,"No Description")
150        CP0_Config1_DL = Param.Unsigned(0,"No Description")
151        CP0_Config1_DA = Param.Unsigned(0,"No Description")
152        CP0_Config1_C2 = Param.Bool(False,"No Description")
153        CP0_Config1_MD = Param.Bool(False,"No Description")
154        CP0_Config1_PC = Param.Bool(False,"No Description")
155        CP0_Config1_WR = Param.Bool(False,"No Description")
156        CP0_Config1_CA = Param.Bool(False,"No Description")
157        CP0_Config1_EP = Param.Bool(False,"No Description")
158        CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
159        CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
160        CP0_Config2_TU = Param.Unsigned(0,"No Description")
161        CP0_Config2_TS = Param.Unsigned(0,"No Description")
162        CP0_Config2_TL = Param.Unsigned(0,"No Description")
163        CP0_Config2_TA = Param.Unsigned(0,"No Description")
164        CP0_Config2_SU = Param.Unsigned(0,"No Description")
165        CP0_Config2_SS = Param.Unsigned(0,"No Description")
166        CP0_Config2_SL = Param.Unsigned(0,"No Description")
167        CP0_Config2_SA = Param.Unsigned(0,"No Description")
168        CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
169        CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
170        CP0_Config3_LPA = Param.Bool(False,"No Description")
171        CP0_Config3_VEIC = Param.Bool(False,"No Description")
172        CP0_Config3_VInt = Param.Bool(False,"No Description")
173        CP0_Config3_SP = Param.Bool(False,"No Description")
174        CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
175        CP0_Config3_SM = Param.Bool(False,"No Description")
176        CP0_Config3_TL = Param.Bool(False,"No Description")
177        CP0_WatchHi_M = Param.Bool(False,"No Description")
178        CP0_PerfCtr_M = Param.Bool(False,"No Description")
179        CP0_PerfCtr_W = Param.Bool(False,"No Description")
180        CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
181        CP0_Config = Param.Unsigned(0,"CP0 Config Register")
182        CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
183        CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
184        CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
185