BaseCPU.py revision 12440 
1# Copyright (c) 2012-2013, 2015-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.SimObject import *
47from m5.defines import buildEnv
48from m5.params import *
49from m5.proxy import *
50
51from XBar import L2XBar
52from InstTracer import InstTracer
53from CPUTracers import ExeTracer
54from MemObject import MemObject
55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60    from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
61    from AlphaInterrupts import AlphaInterrupts
62    from AlphaISA import AlphaISA
63    default_isa_class = AlphaISA
64elif buildEnv['TARGET_ISA'] == 'sparc':
65    from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
66    from SparcInterrupts import SparcInterrupts
67    from SparcISA import SparcISA
68    default_isa_class = SparcISA
69elif buildEnv['TARGET_ISA'] == 'x86':
70    from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
71    from X86LocalApic import X86LocalApic
72    from X86ISA import X86ISA
73    default_isa_class = X86ISA
74elif buildEnv['TARGET_ISA'] == 'mips':
75    from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
76    from MipsInterrupts import MipsInterrupts
77    from MipsISA import MipsISA
78    default_isa_class = MipsISA
79elif buildEnv['TARGET_ISA'] == 'arm':
80    from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
81    from ArmTLB import ArmStage2IMMU, ArmStage2DMMU
82    from ArmInterrupts import ArmInterrupts
83    from ArmISA import ArmISA
84    default_isa_class = ArmISA
85elif buildEnv['TARGET_ISA'] == 'power':
86    from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
87    from PowerInterrupts import PowerInterrupts
88    from PowerISA import PowerISA
89    default_isa_class = PowerISA
90elif buildEnv['TARGET_ISA'] == 'riscv':
91    from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
92    from RiscvInterrupts import RiscvInterrupts
93    from RiscvISA import RiscvISA
94    default_isa_class = RiscvISA
95
96class BaseCPU(MemObject):
97    type = 'BaseCPU'
98    abstract = True
99    cxx_header = "cpu/base.hh"
100
101    cxx_exports = [
102        PyBindMethod("switchOut"),
103        PyBindMethod("takeOverFrom"),
104        PyBindMethod("switchedOut"),
105        PyBindMethod("flushTLBs"),
106        PyBindMethod("totalInsts"),
107        PyBindMethod("scheduleInstStop"),
108        PyBindMethod("scheduleLoadStop"),
109        PyBindMethod("getCurrentInstCount"),
110    ]
111
112    @classmethod
113    def memory_mode(cls):
114        """Which memory mode does this CPU require?"""
115        return 'invalid'
116
117    @classmethod
118    def require_caches(cls):
119        """Does the CPU model require caches?
120
121        Some CPU models might make assumptions that require them to
122        have caches.
123        """
124        return False
125
126    @classmethod
127    def support_take_over(cls):
128        """Does the CPU model support CPU takeOverFrom?"""
129        return False
130
131    def takeOverFrom(self, old_cpu):
132        self._ccObject.takeOverFrom(old_cpu._ccObject)
133
134
135    system = Param.System(Parent.any, "system object")
136    cpu_id = Param.Int(-1, "CPU identifier")
137    socket_id = Param.Unsigned(0, "Physical Socket identifier")
138    numThreads = Param.Unsigned(1, "number of HW thread contexts")
139    pwr_gating_latency = Param.Cycles(300,
140        "Latency to enter power gating state when all contexts are suspended")
141
142    power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\
143        "to the OFF power state after all thread are disabled for "\
144        "pwr_gating_latency cycles")
145
146    function_trace = Param.Bool(False, "Enable function trace")
147    function_trace_start = Param.Tick(0, "Tick to start function trace")
148
149    checker = Param.BaseCPU(NULL, "checker CPU")
150
151    syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry")
152
153    do_checkpoint_insts = Param.Bool(True,
154        "enable checkpoint pseudo instructions")
155    do_statistics_insts = Param.Bool(True,
156        "enable statistics pseudo instructions")
157
158    profile = Param.Latency('0ns', "trace the kernel stack")
159    do_quiesce = Param.Bool(True, "enable quiesce instructions")
160
161    wait_for_remote_gdb = Param.Bool(False,
162        "Wait for a remote GDB connection");
163
164    workload = VectorParam.Process([], "processes to run")
165
166    dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
167    itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
168    if buildEnv['TARGET_ISA'] == 'sparc':
169        interrupts = VectorParam.SparcInterrupts(
170                [], "Interrupt Controller")
171        isa = VectorParam.SparcISA([], "ISA instance")
172    elif buildEnv['TARGET_ISA'] == 'alpha':
173        interrupts = VectorParam.AlphaInterrupts(
174                [], "Interrupt Controller")
175        isa = VectorParam.AlphaISA([], "ISA instance")
176    elif buildEnv['TARGET_ISA'] == 'x86':
177        interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
178        isa = VectorParam.X86ISA([], "ISA instance")
179    elif buildEnv['TARGET_ISA'] == 'mips':
180        interrupts = VectorParam.MipsInterrupts(
181                [], "Interrupt Controller")
182        isa = VectorParam.MipsISA([], "ISA instance")
183    elif buildEnv['TARGET_ISA'] == 'arm':
184        istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
185        dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
186        interrupts = VectorParam.ArmInterrupts(
187                [], "Interrupt Controller")
188        isa = VectorParam.ArmISA([], "ISA instance")
189    elif buildEnv['TARGET_ISA'] == 'power':
190        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
191        interrupts = VectorParam.PowerInterrupts(
192                [], "Interrupt Controller")
193        isa = VectorParam.PowerISA([], "ISA instance")
194    elif buildEnv['TARGET_ISA'] == 'riscv':
195        interrupts = VectorParam.RiscvInterrupts(
196                [], "Interrupt Controller")
197        isa = VectorParam.RiscvISA([], "ISA instance")
198    else:
199        print "Don't know what TLB to use for ISA %s" % \
200            buildEnv['TARGET_ISA']
201        sys.exit(1)
202
203    max_insts_all_threads = Param.Counter(0,
204        "terminate when all threads have reached this inst count")
205    max_insts_any_thread = Param.Counter(0,
206        "terminate when any thread reaches this inst count")
207    simpoint_start_insts = VectorParam.Counter([],
208        "starting instruction counts of simpoints")
209    max_loads_all_threads = Param.Counter(0,
210        "terminate when all threads have reached this load count")
211    max_loads_any_thread = Param.Counter(0,
212        "terminate when any thread reaches this load count")
213    progress_interval = Param.Frequency('0Hz',
214        "frequency to print out the progress message")
215
216    switched_out = Param.Bool(False,
217        "Leave the CPU switched out after startup (used when switching " \
218        "between CPU models)")
219
220    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
221
222    icache_port = MasterPort("Instruction Port")
223    dcache_port = MasterPort("Data Port")
224    _cached_ports = ['icache_port', 'dcache_port']
225
226    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
227        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
228
229    _uncached_slave_ports = []
230    _uncached_master_ports = []
231    if buildEnv['TARGET_ISA'] == 'x86':
232        _uncached_slave_ports += ["interrupts[0].pio",
233                                  "interrupts[0].int_slave"]
234        _uncached_master_ports += ["interrupts[0].int_master"]
235
236    def createInterruptController(self):
237        if buildEnv['TARGET_ISA'] == 'sparc':
238            self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
239        elif buildEnv['TARGET_ISA'] == 'alpha':
240            self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
241        elif buildEnv['TARGET_ISA'] == 'x86':
242            self.apic_clk_domain = DerivedClockDomain(clk_domain =
243                                                      Parent.clk_domain,
244                                                      clk_divider = 16)
245            self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
246                                           pio_addr=0x2000000000000000)
247                               for i in xrange(self.numThreads)]
248            _localApic = self.interrupts
249        elif buildEnv['TARGET_ISA'] == 'mips':
250            self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
251        elif buildEnv['TARGET_ISA'] == 'arm':
252            self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
253        elif buildEnv['TARGET_ISA'] == 'power':
254            self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
255        elif buildEnv['TARGET_ISA'] == 'riscv':
256            self.interrupts = \
257                [RiscvInterrupts() for i in xrange(self.numThreads)]
258        else:
259            print "Don't know what Interrupt Controller to use for ISA %s" % \
260                buildEnv['TARGET_ISA']
261            sys.exit(1)
262
263    def connectCachedPorts(self, bus):
264        for p in self._cached_ports:
265            exec('self.%s = bus.slave' % p)
266
267    def connectUncachedPorts(self, bus):
268        for p in self._uncached_slave_ports:
269            exec('self.%s = bus.master' % p)
270        for p in self._uncached_master_ports:
271            exec('self.%s = bus.slave' % p)
272
273    def connectAllPorts(self, cached_bus, uncached_bus = None):
274        self.connectCachedPorts(cached_bus)
275        if not uncached_bus:
276            uncached_bus = cached_bus
277        self.connectUncachedPorts(uncached_bus)
278
279    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
280        self.icache = ic
281        self.dcache = dc
282        self.icache_port = ic.cpu_side
283        self.dcache_port = dc.cpu_side
284        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
285        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
286            if iwc and dwc:
287                self.itb_walker_cache = iwc
288                self.dtb_walker_cache = dwc
289                self.itb.walker.port = iwc.cpu_side
290                self.dtb.walker.port = dwc.cpu_side
291                self._cached_ports += ["itb_walker_cache.mem_side", \
292                                       "dtb_walker_cache.mem_side"]
293            else:
294                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
295
296            # Checker doesn't need its own tlb caches because it does
297            # functional accesses only
298            if self.checker != NULL:
299                self._cached_ports += ["checker.itb.walker.port", \
300                                       "checker.dtb.walker.port"]
301
302    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
303                                  xbar=None):
304        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
305        self.toL2Bus = xbar if xbar else L2XBar()
306        self.connectCachedPorts(self.toL2Bus)
307        self.l2cache = l2c
308        self.toL2Bus.master = self.l2cache.cpu_side
309        self._cached_ports = ['l2cache.mem_side']
310
311    def createThreads(self):
312        # If no ISAs have been created, assume that the user wants the
313        # default ISA.
314        if len(self.isa) == 0:
315            self.isa = [ default_isa_class() for i in xrange(self.numThreads) ]
316        else:
317            if len(self.isa) != int(self.numThreads):
318                raise RuntimeError("Number of ISA instances doesn't "
319                                   "match thread count")
320        if self.checker != NULL:
321            self.checker.createThreads()
322
323    def addCheckerCpu(self):
324        pass
325