BaseCPU.py revision 10037:5cac77888310 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
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13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
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39#
40# Authors: Nathan Binkert
41#          Rick Strong
42#          Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from ClockDomain import *
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59    from AlphaTLB import AlphaDTB, AlphaITB
60    from AlphaInterrupts import AlphaInterrupts
61    from AlphaISA import AlphaISA
62    isa_class = AlphaISA
63elif buildEnv['TARGET_ISA'] == 'sparc':
64    from SparcTLB import SparcTLB
65    from SparcInterrupts import SparcInterrupts
66    from SparcISA import SparcISA
67    isa_class = SparcISA
68elif buildEnv['TARGET_ISA'] == 'x86':
69    from X86TLB import X86TLB
70    from X86LocalApic import X86LocalApic
71    from X86ISA import X86ISA
72    isa_class = X86ISA
73elif buildEnv['TARGET_ISA'] == 'mips':
74    from MipsTLB import MipsTLB
75    from MipsInterrupts import MipsInterrupts
76    from MipsISA import MipsISA
77    isa_class = MipsISA
78elif buildEnv['TARGET_ISA'] == 'arm':
79    from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
80    from ArmInterrupts import ArmInterrupts
81    from ArmISA import ArmISA
82    isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84    from PowerTLB import PowerTLB
85    from PowerInterrupts import PowerInterrupts
86    from PowerISA import PowerISA
87    isa_class = PowerISA
88
89class BaseCPU(MemObject):
90    type = 'BaseCPU'
91    abstract = True
92    cxx_header = "cpu/base.hh"
93
94    @classmethod
95    def export_methods(cls, code):
96        code('''
97    void switchOut();
98    void takeOverFrom(BaseCPU *cpu);
99    bool switchedOut();
100    void flushTLBs();
101    Counter totalInsts();
102    void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
103    void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
104''')
105
106    @classmethod
107    def memory_mode(cls):
108        """Which memory mode does this CPU require?"""
109        return 'invalid'
110
111    @classmethod
112    def require_caches(cls):
113        """Does the CPU model require caches?
114
115        Some CPU models might make assumptions that require them to
116        have caches.
117        """
118        return False
119
120    @classmethod
121    def support_take_over(cls):
122        """Does the CPU model support CPU takeOverFrom?"""
123        return False
124
125    def takeOverFrom(self, old_cpu):
126        self._ccObject.takeOverFrom(old_cpu._ccObject)
127
128
129    system = Param.System(Parent.any, "system object")
130    cpu_id = Param.Int(-1, "CPU identifier")
131    numThreads = Param.Unsigned(1, "number of HW thread contexts")
132
133    function_trace = Param.Bool(False, "Enable function trace")
134    function_trace_start = Param.Tick(0, "Tick to start function trace")
135
136    checker = Param.BaseCPU(NULL, "checker CPU")
137
138    do_checkpoint_insts = Param.Bool(True,
139        "enable checkpoint pseudo instructions")
140    do_statistics_insts = Param.Bool(True,
141        "enable statistics pseudo instructions")
142
143    profile = Param.Latency('0ns', "trace the kernel stack")
144    do_quiesce = Param.Bool(True, "enable quiesce instructions")
145
146    workload = VectorParam.Process([], "processes to run")
147
148    if buildEnv['TARGET_ISA'] == 'sparc':
149        dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
150        itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
151        interrupts = Param.SparcInterrupts(
152                NULL, "Interrupt Controller")
153        isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
154    elif buildEnv['TARGET_ISA'] == 'alpha':
155        dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
156        itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
157        interrupts = Param.AlphaInterrupts(
158                NULL, "Interrupt Controller")
159        isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
160    elif buildEnv['TARGET_ISA'] == 'x86':
161        dtb = Param.X86TLB(X86TLB(), "Data TLB")
162        itb = Param.X86TLB(X86TLB(), "Instruction TLB")
163        interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
164        isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
165    elif buildEnv['TARGET_ISA'] == 'mips':
166        dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
167        itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
168        interrupts = Param.MipsInterrupts(
169                NULL, "Interrupt Controller")
170        isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
171    elif buildEnv['TARGET_ISA'] == 'arm':
172        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
173        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
174        istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
175        dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
176        interrupts = Param.ArmInterrupts(
177                NULL, "Interrupt Controller")
178        isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
179    elif buildEnv['TARGET_ISA'] == 'power':
180        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
181        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
182        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
183        interrupts = Param.PowerInterrupts(
184                NULL, "Interrupt Controller")
185        isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
186    else:
187        print "Don't know what TLB to use for ISA %s" % \
188            buildEnv['TARGET_ISA']
189        sys.exit(1)
190
191    max_insts_all_threads = Param.Counter(0,
192        "terminate when all threads have reached this inst count")
193    max_insts_any_thread = Param.Counter(0,
194        "terminate when any thread reaches this inst count")
195    simpoint_start_insts = VectorParam.Counter([],
196        "starting instruction counts of simpoints")
197    max_loads_all_threads = Param.Counter(0,
198        "terminate when all threads have reached this load count")
199    max_loads_any_thread = Param.Counter(0,
200        "terminate when any thread reaches this load count")
201    progress_interval = Param.Frequency('0Hz',
202        "frequency to print out the progress message")
203
204    switched_out = Param.Bool(False,
205        "Leave the CPU switched out after startup (used when switching " \
206        "between CPU models)")
207
208    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
209
210    icache_port = MasterPort("Instruction Port")
211    dcache_port = MasterPort("Data Port")
212    _cached_ports = ['icache_port', 'dcache_port']
213
214    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
215        _cached_ports += ["itb.walker.port", "dtb.walker.port"]
216        if buildEnv['TARGET_ISA'] in ['arm']:
217            _cached_ports += ["istage2_mmu.stage2_tlb.walker.port",
218                              "dstage2_mmu.stage2_tlb.walker.port"]
219
220    _uncached_slave_ports = []
221    _uncached_master_ports = []
222    if buildEnv['TARGET_ISA'] == 'x86':
223        _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
224        _uncached_master_ports += ["interrupts.int_master"]
225
226    def createInterruptController(self):
227        if buildEnv['TARGET_ISA'] == 'sparc':
228            self.interrupts = SparcInterrupts()
229        elif buildEnv['TARGET_ISA'] == 'alpha':
230            self.interrupts = AlphaInterrupts()
231        elif buildEnv['TARGET_ISA'] == 'x86':
232            self.apic_clk_domain = DerivedClockDomain(clk_domain =
233                                                      Parent.clk_domain,
234                                                      clk_divider = 16)
235            self.interrupts = X86LocalApic(clk_domain = self.apic_clk_domain,
236                                           pio_addr=0x2000000000000000)
237            _localApic = self.interrupts
238        elif buildEnv['TARGET_ISA'] == 'mips':
239            self.interrupts = MipsInterrupts()
240        elif buildEnv['TARGET_ISA'] == 'arm':
241            self.interrupts = ArmInterrupts()
242        elif buildEnv['TARGET_ISA'] == 'power':
243            self.interrupts = PowerInterrupts()
244        else:
245            print "Don't know what Interrupt Controller to use for ISA %s" % \
246                buildEnv['TARGET_ISA']
247            sys.exit(1)
248
249    def connectCachedPorts(self, bus):
250        for p in self._cached_ports:
251            exec('self.%s = bus.slave' % p)
252
253    def connectUncachedPorts(self, bus):
254        for p in self._uncached_slave_ports:
255            exec('self.%s = bus.master' % p)
256        for p in self._uncached_master_ports:
257            exec('self.%s = bus.slave' % p)
258
259    def connectAllPorts(self, cached_bus, uncached_bus = None):
260        self.connectCachedPorts(cached_bus)
261        if not uncached_bus:
262            uncached_bus = cached_bus
263        self.connectUncachedPorts(uncached_bus)
264
265    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
266        self.icache = ic
267        self.dcache = dc
268        self.icache_port = ic.cpu_side
269        self.dcache_port = dc.cpu_side
270        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
271        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
272            if iwc and dwc:
273                self.itb_walker_cache = iwc
274                self.dtb_walker_cache = dwc
275                if buildEnv['TARGET_ISA'] in ['arm']:
276                    self.itb_walker_cache_bus = CoherentBus()
277                    self.dtb_walker_cache_bus = CoherentBus()
278                    self.itb_walker_cache_bus.master = iwc.cpu_side
279                    self.dtb_walker_cache_bus.master = dwc.cpu_side
280                    self.itb.walker.port = self.itb_walker_cache_bus.slave
281                    self.dtb.walker.port = self.dtb_walker_cache_bus.slave
282                    self.istage2_mmu.stage2_tlb.walker.port = self.itb_walker_cache_bus.slave
283                    self.dstage2_mmu.stage2_tlb.walker.port = self.dtb_walker_cache_bus.slave
284                else:
285                    self.itb.walker.port = iwc.cpu_side
286                    self.dtb.walker.port = dwc.cpu_side
287                self._cached_ports += ["itb_walker_cache.mem_side", \
288                                       "dtb_walker_cache.mem_side"]
289            else:
290                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
291
292                if buildEnv['TARGET_ISA'] in ['arm']:
293                    self._cached_ports += ["istage2_mmu.stage2_tlb.walker.port", \
294                                           "dstage2_mmu.stage2_tlb.walker.port"]
295
296            # Checker doesn't need its own tlb caches because it does
297            # functional accesses only
298            if self.checker != NULL:
299                self._cached_ports += ["checker.itb.walker.port", \
300                                       "checker.dtb.walker.port"]
301                if buildEnv['TARGET_ISA'] in ['arm']:
302                    self._cached_ports += ["checker.istage2_mmu.stage2_tlb.walker.port", \
303                                           "checker.dstage2_mmu.stage2_tlb.walker.port"]
304
305    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
306        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
307        # Set a width of 32 bytes (256-bits), which is four times that
308        # of the default bus. The clock of the CPU is inherited by
309        # default.
310        self.toL2Bus = CoherentBus(width = 32)
311        self.connectCachedPorts(self.toL2Bus)
312        self.l2cache = l2c
313        self.toL2Bus.master = self.l2cache.cpu_side
314        self._cached_ports = ['l2cache.mem_side']
315
316    def createThreads(self):
317        self.isa = [ isa_class() for i in xrange(self.numThreads) ]
318        if self.checker != NULL:
319            self.checker.createThreads()
320
321    def addCheckerCpu(self):
322        pass
323