BaseCPU.py revision 9793
18839Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 434486Sbinkertn@umich.edu 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 466654Snate@binkert.orgfrom m5.defines import buildEnv 473102SN/Afrom m5.params import * 483102SN/Afrom m5.proxy import * 496654Snate@binkert.org 509036Sandreas.hansson@arm.comfrom Bus import CoherentBus 514776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 524776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 536654Snate@binkert.orgfrom MemObject import MemObject 549480Snilay@cs.wisc.edufrom BranchPredictor import BranchPredictor 559793Sakash.bagdia@arm.comfrom ClockDomain import * 562667SN/A 574776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 584776Sgblack@eecs.umich.edu 596654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 606023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 618745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 629384SAndreas.Sandberg@arm.com from AlphaISA import AlphaISA 639384SAndreas.Sandberg@arm.com isa_class = AlphaISA 646654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 656022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 668745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 679384SAndreas.Sandberg@arm.com from SparcISA import SparcISA 689384SAndreas.Sandberg@arm.com isa_class = SparcISA 696654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 706022Sgblack@eecs.umich.edu from X86TLB import X86TLB 718745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 729384SAndreas.Sandberg@arm.com from X86ISA import X86ISA 739384SAndreas.Sandberg@arm.com isa_class = X86ISA 746654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 756022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 768745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 779384SAndreas.Sandberg@arm.com from MipsISA import MipsISA 789384SAndreas.Sandberg@arm.com isa_class = MipsISA 796654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 806116Snate@binkert.org from ArmTLB import ArmTLB 818745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 829384SAndreas.Sandberg@arm.com from ArmISA import ArmISA 839384SAndreas.Sandberg@arm.com isa_class = ArmISA 846691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 856691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 868745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 879384SAndreas.Sandberg@arm.com from PowerISA import PowerISA 889384SAndreas.Sandberg@arm.com isa_class = PowerISA 894486Sbinkertn@umich.edu 905529Snate@binkert.orgclass BaseCPU(MemObject): 911366SN/A type = 'BaseCPU' 921310SN/A abstract = True 939338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 949254SAndreas.Sandberg@arm.com 959254SAndreas.Sandberg@arm.com @classmethod 969254SAndreas.Sandberg@arm.com def export_methods(cls, code): 979254SAndreas.Sandberg@arm.com code(''' 989254SAndreas.Sandberg@arm.com void switchOut(); 999254SAndreas.Sandberg@arm.com void takeOverFrom(BaseCPU *cpu); 1009430SAndreas.Sandberg@ARM.com bool switchedOut(); 1019446SAndreas.Sandberg@ARM.com void flushTLBs(); 1029650Stimothy.jones@arm.com Counter totalInsts(); 1039749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 1049749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 1059254SAndreas.Sandberg@arm.com''') 1069254SAndreas.Sandberg@arm.com 1079518SAndreas.Sandberg@ARM.com @classmethod 1089518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1099518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1109518SAndreas.Sandberg@ARM.com return 'invalid' 1119518SAndreas.Sandberg@ARM.com 1129518SAndreas.Sandberg@ARM.com @classmethod 1139518SAndreas.Sandberg@ARM.com def require_caches(cls): 1149518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1159518SAndreas.Sandberg@ARM.com 1169518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1179518SAndreas.Sandberg@ARM.com have caches. 1189518SAndreas.Sandberg@ARM.com """ 1199518SAndreas.Sandberg@ARM.com return False 1209518SAndreas.Sandberg@ARM.com 1219518SAndreas.Sandberg@ARM.com @classmethod 1229518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1239518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1249518SAndreas.Sandberg@ARM.com return False 1259518SAndreas.Sandberg@ARM.com 1269254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1279254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1289254SAndreas.Sandberg@arm.com 1299254SAndreas.Sandberg@arm.com 1302901SN/A system = Param.System(Parent.any, "system object") 1315712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 1325529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 1335529Snate@binkert.org 1345529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1359161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1365529Snate@binkert.org 1375821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1383170SN/A 1395780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1405780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1415780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1425780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1435780Ssteve.reinhardt@amd.com 1448784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1458784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1468784Sgblack@eecs.umich.edu 1478793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1481310SN/A 1496654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 1506022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1516022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1528745Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 1538863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1549384SAndreas.Sandberg@arm.com isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 1556654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1566023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1576023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1588745Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 1598863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1609384SAndreas.Sandberg@arm.com isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 1616654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1626022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1636022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1648863Snilay@cs.wisc.edu interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 1659384SAndreas.Sandberg@arm.com isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 1666654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1676022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1686022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1698745Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1708863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1719384SAndreas.Sandberg@arm.com isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 1726654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1736116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1746116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1758745Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1768863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1779384SAndreas.Sandberg@arm.com isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 1786691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1796691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1806691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1816691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1828745Sgblack@eecs.umich.edu interrupts = Param.PowerInterrupts( 1838863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1849384SAndreas.Sandberg@arm.com isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 1854997Sgblack@eecs.umich.edu else: 1864997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1876654Snate@binkert.org buildEnv['TARGET_ISA'] 1884997Sgblack@eecs.umich.edu sys.exit(1) 1894997Sgblack@eecs.umich.edu 1901310SN/A max_insts_all_threads = Param.Counter(0, 1911310SN/A "terminate when all threads have reached this inst count") 1921310SN/A max_insts_any_thread = Param.Counter(0, 1931310SN/A "terminate when any thread reaches this inst count") 1949647Sdam.sunwoo@arm.com simpoint_start_insts = VectorParam.Counter([], 1959647Sdam.sunwoo@arm.com "starting instruction counts of simpoints") 1961310SN/A max_loads_all_threads = Param.Counter(0, 1971310SN/A "terminate when all threads have reached this load count") 1981310SN/A max_loads_any_thread = Param.Counter(0, 1991310SN/A "terminate when any thread reaches this load count") 2009180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 2019180Sandreas.hansson@arm.com "frequency to print out the progress message") 2021310SN/A 2039433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 2049433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 2059433SAndreas.Sandberg@ARM.com "between CPU models)") 2061634SN/A 2074776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2084776Sgblack@eecs.umich.edu 2098839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2108839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2118707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2128707Sandreas.hansson@arm.com 2139480Snilay@cs.wisc.edu branchPred = Param.BranchPredictor(NULL, "Branch Predictor") 2149480Snilay@cs.wisc.edu 2158756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2168707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2177876Sgblack@eecs.umich.edu 2188839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2198839Sandreas.hansson@arm.com _uncached_master_ports = [] 2208745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 2218839Sandreas.hansson@arm.com _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 2228839Sandreas.hansson@arm.com _uncached_master_ports += ["interrupts.int_master"] 2232998SN/A 2248863Snilay@cs.wisc.edu def createInterruptController(self): 2258863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 2268863Snilay@cs.wisc.edu self.interrupts = SparcInterrupts() 2278863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 2288863Snilay@cs.wisc.edu self.interrupts = AlphaInterrupts() 2298863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2309793Sakash.bagdia@arm.com self.apic_clk_domain = DerivedClockDomain(clk_domain = 2319793Sakash.bagdia@arm.com Parent.clk_domain, 2329793Sakash.bagdia@arm.com clk_divider = 16) 2339793Sakash.bagdia@arm.com self.interrupts = X86LocalApic(clk_domain = self.apic_clk_domain, 2349544Sandreas.hansson@arm.com pio_addr=0x2000000000000000) 2359544Sandreas.hansson@arm.com _localApic = self.interrupts 2368863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 2378863Snilay@cs.wisc.edu self.interrupts = MipsInterrupts() 2388863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 2398863Snilay@cs.wisc.edu self.interrupts = ArmInterrupts() 2408863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 2418863Snilay@cs.wisc.edu self.interrupts = PowerInterrupts() 2428863Snilay@cs.wisc.edu else: 2438863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2448863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 2458863Snilay@cs.wisc.edu sys.exit(1) 2468863Snilay@cs.wisc.edu 2477876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2487876Sgblack@eecs.umich.edu for p in self._cached_ports: 2498839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2507404SAli.Saidi@ARM.com 2517876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2528839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2538839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2548839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2558839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2567876Sgblack@eecs.umich.edu 2577876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2587876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2597876Sgblack@eecs.umich.edu if not uncached_bus: 2607876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2617876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2622998SN/A 2637868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2642998SN/A self.icache = ic 2652998SN/A self.dcache = dc 2662998SN/A self.icache_port = ic.cpu_side 2672998SN/A self.dcache_port = dc.cpu_side 2687876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2698796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2708796Sgblack@eecs.umich.edu if iwc and dwc: 2718796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2728796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 2738796Sgblack@eecs.umich.edu self.itb.walker.port = iwc.cpu_side 2748796Sgblack@eecs.umich.edu self.dtb.walker.port = dwc.cpu_side 2758796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2768796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2778796Sgblack@eecs.umich.edu else: 2788796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2798887Sgeoffrey.blake@arm.com 2808809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 2818809Sgblack@eecs.umich.edu # functional accesses only 2828887Sgeoffrey.blake@arm.com if self.checker != NULL: 2838809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 2848809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 2852998SN/A 2867868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 2877868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 2889788Sakash.bagdia@arm.com # Set a width of 32 bytes (256-bits), which is four times that 2899788Sakash.bagdia@arm.com # of the default bus. The clock of the CPU is inherited by 2909788Sakash.bagdia@arm.com # default. 2919788Sakash.bagdia@arm.com self.toL2Bus = CoherentBus(width = 32) 2927876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 2932998SN/A self.l2cache = l2c 2948839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 2957876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 2968887Sgeoffrey.blake@arm.com 2979384SAndreas.Sandberg@arm.com def createThreads(self): 2989384SAndreas.Sandberg@arm.com self.isa = [ isa_class() for i in xrange(self.numThreads) ] 2999384SAndreas.Sandberg@arm.com if self.checker != NULL: 3009384SAndreas.Sandberg@arm.com self.checker.createThreads() 3019384SAndreas.Sandberg@arm.com 3028887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 3038887Sgeoffrey.blake@arm.com pass 304