BaseCPU.py revision 9650
15222Sksewell@umich.edu# Copyright (c) 2012 ARM Limited 25254Sksewell@umich.edu# All rights reserved. 35254Sksewell@umich.edu# 45222Sksewell@umich.edu# The license below extends only to copyright in the software and shall 55254Sksewell@umich.edu# not be construed as granting a license to any other intellectual 65254Sksewell@umich.edu# property including but not limited to intellectual property relating 75254Sksewell@umich.edu# to a hardware implementation of the functionality of the software 85254Sksewell@umich.edu# licensed hereunder. You may use the software subject to the license 95254Sksewell@umich.edu# terms below provided that you ensure that this notice is replicated 105254Sksewell@umich.edu# unmodified and in its entirety in all distributions of the software, 115254Sksewell@umich.edu# modified or unmodified, in source code or in binary form. 125254Sksewell@umich.edu# 135254Sksewell@umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 145254Sksewell@umich.edu# Copyright (c) 2011 Regents of the University of California 155222Sksewell@umich.edu# All rights reserved. 165254Sksewell@umich.edu# 175254Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 185254Sksewell@umich.edu# modification, are permitted provided that the following conditions are 195254Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 205254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 215254Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 225254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 235254Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 245254Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 255254Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 265254Sksewell@umich.edu# this software without specific prior written permission. 275222Sksewell@umich.edu# 285254Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295222Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305222Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315222Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325222Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335222Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345222Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355222Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365222Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375222Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385222Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395222Sksewell@umich.edu# 405222Sksewell@umich.edu# Authors: Nathan Binkert 415222Sksewell@umich.edu# Rick Strong 425222Sksewell@umich.edu# Andreas Hansson 435222Sksewell@umich.edu 445222Sksewell@umich.eduimport sys 456378Sgblack@eecs.umich.edu 466378Sgblack@eecs.umich.edufrom m5.defines import buildEnv 475222Sksewell@umich.edufrom m5.params import * 485222Sksewell@umich.edufrom m5.proxy import * 495222Sksewell@umich.edu 505222Sksewell@umich.edufrom Bus import CoherentBus 515222Sksewell@umich.edufrom InstTracer import InstTracer 525222Sksewell@umich.edufrom ExeTracer import ExeTracer 535222Sksewell@umich.edufrom MemObject import MemObject 545222Sksewell@umich.edufrom BranchPredictor import BranchPredictor 555222Sksewell@umich.edu 565222Sksewell@umich.edudefault_tracer = ExeTracer() 578706Sandreas.hansson@arm.com 585222Sksewell@umich.eduif buildEnv['TARGET_ISA'] == 'alpha': 598706Sandreas.hansson@arm.com from AlphaTLB import AlphaDTB, AlphaITB 605222Sksewell@umich.edu from AlphaInterrupts import AlphaInterrupts 615222Sksewell@umich.edu from AlphaISA import AlphaISA 625222Sksewell@umich.edu isa_class = AlphaISA 635222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 645222Sksewell@umich.edu from SparcTLB import SparcTLB 655222Sksewell@umich.edu from SparcInterrupts import SparcInterrupts 665222Sksewell@umich.edu from SparcISA import SparcISA 675222Sksewell@umich.edu isa_class = SparcISA 685222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 695222Sksewell@umich.edu from X86TLB import X86TLB 705222Sksewell@umich.edu from X86LocalApic import X86LocalApic 715222Sksewell@umich.edu from X86ISA import X86ISA 725222Sksewell@umich.edu isa_class = X86ISA 735222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 748706Sandreas.hansson@arm.com from MipsTLB import MipsTLB 755222Sksewell@umich.edu from MipsInterrupts import MipsInterrupts 768706Sandreas.hansson@arm.com from MipsISA import MipsISA 775222Sksewell@umich.edu isa_class = MipsISA 785222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 795222Sksewell@umich.edu from ArmTLB import ArmTLB 805222Sksewell@umich.edu from ArmInterrupts import ArmInterrupts 815222Sksewell@umich.edu from ArmISA import ArmISA 825222Sksewell@umich.edu isa_class = ArmISA 835222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'power': 845222Sksewell@umich.edu from PowerTLB import PowerTLB 855222Sksewell@umich.edu from PowerInterrupts import PowerInterrupts 865222Sksewell@umich.edu from PowerISA import PowerISA 875222Sksewell@umich.edu isa_class = PowerISA 885222Sksewell@umich.edu 895222Sksewell@umich.educlass BaseCPU(MemObject): 905222Sksewell@umich.edu type = 'BaseCPU' 915222Sksewell@umich.edu abstract = True 925222Sksewell@umich.edu cxx_header = "cpu/base.hh" 935222Sksewell@umich.edu 945222Sksewell@umich.edu @classmethod 955222Sksewell@umich.edu def export_methods(cls, code): 965222Sksewell@umich.edu code(''' 975222Sksewell@umich.edu void switchOut(); 985222Sksewell@umich.edu void takeOverFrom(BaseCPU *cpu); 995222Sksewell@umich.edu bool switchedOut(); 1005222Sksewell@umich.edu void flushTLBs(); 1015222Sksewell@umich.edu Counter totalInsts(); 1025222Sksewell@umich.edu''') 1035222Sksewell@umich.edu 1045222Sksewell@umich.edu @classmethod 1055222Sksewell@umich.edu def memory_mode(cls): 1065222Sksewell@umich.edu """Which memory mode does this CPU require?""" 1075222Sksewell@umich.edu return 'invalid' 1085222Sksewell@umich.edu 1095222Sksewell@umich.edu @classmethod 1105222Sksewell@umich.edu def require_caches(cls): 1115222Sksewell@umich.edu """Does the CPU model require caches? 1125222Sksewell@umich.edu 1135222Sksewell@umich.edu Some CPU models might make assumptions that require them to 1145222Sksewell@umich.edu have caches. 1155222Sksewell@umich.edu """ 1165222Sksewell@umich.edu return False 1175222Sksewell@umich.edu 1185222Sksewell@umich.edu @classmethod 1195222Sksewell@umich.edu def support_take_over(cls): 1205222Sksewell@umich.edu """Does the CPU model support CPU takeOverFrom?""" 1215222Sksewell@umich.edu return False 1225222Sksewell@umich.edu 1235222Sksewell@umich.edu def takeOverFrom(self, old_cpu): 1245222Sksewell@umich.edu self._ccObject.takeOverFrom(old_cpu._ccObject) 1255222Sksewell@umich.edu 1265222Sksewell@umich.edu 1275222Sksewell@umich.edu system = Param.System(Parent.any, "system object") 1285222Sksewell@umich.edu cpu_id = Param.Int(-1, "CPU identifier") 1295222Sksewell@umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 1305222Sksewell@umich.edu 1315222Sksewell@umich.edu function_trace = Param.Bool(False, "Enable function trace") 1325222Sksewell@umich.edu function_trace_start = Param.Tick(0, "Tick to start function trace") 1335222Sksewell@umich.edu 1345222Sksewell@umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1355222Sksewell@umich.edu 1365222Sksewell@umich.edu do_checkpoint_insts = Param.Bool(True, 1375222Sksewell@umich.edu "enable checkpoint pseudo instructions") 1385222Sksewell@umich.edu do_statistics_insts = Param.Bool(True, 1395222Sksewell@umich.edu "enable statistics pseudo instructions") 1405222Sksewell@umich.edu 1415222Sksewell@umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1425222Sksewell@umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1435222Sksewell@umich.edu 1445222Sksewell@umich.edu workload = VectorParam.Process([], "processes to run") 1455222Sksewell@umich.edu 1465222Sksewell@umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 1475222Sksewell@umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1485222Sksewell@umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1495222Sksewell@umich.edu interrupts = Param.SparcInterrupts( 1505222Sksewell@umich.edu NULL, "Interrupt Controller") 1515222Sksewell@umich.edu isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 1525222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 1535222Sksewell@umich.edu dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1545222Sksewell@umich.edu itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1555222Sksewell@umich.edu interrupts = Param.AlphaInterrupts( 1565222Sksewell@umich.edu NULL, "Interrupt Controller") 1575222Sksewell@umich.edu isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 1585222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1595222Sksewell@umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1605222Sksewell@umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1615222Sksewell@umich.edu interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 1625222Sksewell@umich.edu isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 1635222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1645222Sksewell@umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1655222Sksewell@umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1665222Sksewell@umich.edu interrupts = Param.MipsInterrupts( 1675222Sksewell@umich.edu NULL, "Interrupt Controller") 1685222Sksewell@umich.edu isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 1695222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1705222Sksewell@umich.edu dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1715222Sksewell@umich.edu itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1725222Sksewell@umich.edu interrupts = Param.ArmInterrupts( 1735222Sksewell@umich.edu NULL, "Interrupt Controller") 1745222Sksewell@umich.edu isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 1755222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'power': 1765222Sksewell@umich.edu UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1775222Sksewell@umich.edu dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1785222Sksewell@umich.edu itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1795222Sksewell@umich.edu interrupts = Param.PowerInterrupts( 1805222Sksewell@umich.edu NULL, "Interrupt Controller") 1815222Sksewell@umich.edu isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 1825222Sksewell@umich.edu else: 1835222Sksewell@umich.edu print "Don't know what TLB to use for ISA %s" % \ 1845222Sksewell@umich.edu buildEnv['TARGET_ISA'] 1855222Sksewell@umich.edu sys.exit(1) 1865222Sksewell@umich.edu 1875222Sksewell@umich.edu max_insts_all_threads = Param.Counter(0, 1885222Sksewell@umich.edu "terminate when all threads have reached this inst count") 1895222Sksewell@umich.edu max_insts_any_thread = Param.Counter(0, 1905222Sksewell@umich.edu "terminate when any thread reaches this inst count") 1915222Sksewell@umich.edu simpoint_start_insts = VectorParam.Counter([], 1925222Sksewell@umich.edu "starting instruction counts of simpoints") 1935222Sksewell@umich.edu max_loads_all_threads = Param.Counter(0, 1945222Sksewell@umich.edu "terminate when all threads have reached this load count") 1955222Sksewell@umich.edu max_loads_any_thread = Param.Counter(0, 1965222Sksewell@umich.edu "terminate when any thread reaches this load count") 1975222Sksewell@umich.edu progress_interval = Param.Frequency('0Hz', 1985222Sksewell@umich.edu "frequency to print out the progress message") 1995222Sksewell@umich.edu 2005222Sksewell@umich.edu switched_out = Param.Bool(False, 2015222Sksewell@umich.edu "Leave the CPU switched out after startup (used when switching " \ 2025222Sksewell@umich.edu "between CPU models)") 2035222Sksewell@umich.edu 2045222Sksewell@umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2055222Sksewell@umich.edu 2065222Sksewell@umich.edu icache_port = MasterPort("Instruction Port") 2075222Sksewell@umich.edu dcache_port = MasterPort("Data Port") 2085222Sksewell@umich.edu _cached_ports = ['icache_port', 'dcache_port'] 2095222Sksewell@umich.edu 2105222Sksewell@umich.edu branchPred = Param.BranchPredictor(NULL, "Branch Predictor") 2115222Sksewell@umich.edu 2125222Sksewell@umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2135222Sksewell@umich.edu _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2145222Sksewell@umich.edu 2155222Sksewell@umich.edu _uncached_slave_ports = [] 2165222Sksewell@umich.edu _uncached_master_ports = [] 2175222Sksewell@umich.edu if buildEnv['TARGET_ISA'] == 'x86': 2185222Sksewell@umich.edu _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 2195222Sksewell@umich.edu _uncached_master_ports += ["interrupts.int_master"] 2205222Sksewell@umich.edu 2215222Sksewell@umich.edu def createInterruptController(self): 2225222Sksewell@umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 2235222Sksewell@umich.edu self.interrupts = SparcInterrupts() 2245222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 2255222Sksewell@umich.edu self.interrupts = AlphaInterrupts() 2265222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 2275222Sksewell@umich.edu self.interrupts = X86LocalApic(clock = Parent.clock * 16, 2285222Sksewell@umich.edu pio_addr=0x2000000000000000) 2295222Sksewell@umich.edu _localApic = self.interrupts 2305222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 2315222Sksewell@umich.edu self.interrupts = MipsInterrupts() 2325222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 2335222Sksewell@umich.edu self.interrupts = ArmInterrupts() 2346378Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'power': 2355222Sksewell@umich.edu self.interrupts = PowerInterrupts() 2365222Sksewell@umich.edu else: 237 print "Don't know what Interrupt Controller to use for ISA %s" % \ 238 buildEnv['TARGET_ISA'] 239 sys.exit(1) 240 241 def connectCachedPorts(self, bus): 242 for p in self._cached_ports: 243 exec('self.%s = bus.slave' % p) 244 245 def connectUncachedPorts(self, bus): 246 for p in self._uncached_slave_ports: 247 exec('self.%s = bus.master' % p) 248 for p in self._uncached_master_ports: 249 exec('self.%s = bus.slave' % p) 250 251 def connectAllPorts(self, cached_bus, uncached_bus = None): 252 self.connectCachedPorts(cached_bus) 253 if not uncached_bus: 254 uncached_bus = cached_bus 255 self.connectUncachedPorts(uncached_bus) 256 257 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 258 self.icache = ic 259 self.dcache = dc 260 self.icache_port = ic.cpu_side 261 self.dcache_port = dc.cpu_side 262 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 263 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 264 if iwc and dwc: 265 self.itb_walker_cache = iwc 266 self.dtb_walker_cache = dwc 267 self.itb.walker.port = iwc.cpu_side 268 self.dtb.walker.port = dwc.cpu_side 269 self._cached_ports += ["itb_walker_cache.mem_side", \ 270 "dtb_walker_cache.mem_side"] 271 else: 272 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 273 274 # Checker doesn't need its own tlb caches because it does 275 # functional accesses only 276 if self.checker != NULL: 277 self._cached_ports += ["checker.itb.walker.port", \ 278 "checker.dtb.walker.port"] 279 280 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 281 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 282 # Override the default bus clock of 1 GHz and uses the CPU 283 # clock for the L1-to-L2 bus, and also set a width of 32 bytes 284 # (256-bits), which is four times that of the default bus. 285 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) 286 self.connectCachedPorts(self.toL2Bus) 287 self.l2cache = l2c 288 self.toL2Bus.master = self.l2cache.cpu_side 289 self._cached_ports = ['l2cache.mem_side'] 290 291 def createThreads(self): 292 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 293 if self.checker != NULL: 294 self.checker.createThreads() 295 296 def addCheckerCpu(self): 297 pass 298